书籍详情
射频电路和射频集成电路设计中的关键课题
作者：RICHARD CHI-HSI LI
出版社：高等教育出版社
出版时间：2005-02-01
ISBN：9787040159585
定价：¥40.10
购买这本书可以去
内容简介
《射频电路和射频集成电路设计中的关键课题》总共十二章，涵盖六个关键性的课题：1）阻抗匹配；2）射频接地；3）单端和差分线路；4）误差分析；5）展望射频集成电路设计；6）射频电路的基本参数和指标。射频电路设计中最大的特点是阻抗匹配。没有阻抗匹配的电路设计就不是射频电路设计。阻抗匹配也是射频电路设计和数码电路设计的主要差別之处。由于它的重要性， 《射频电路和射频集成电路设计中的关键课题》的第一章和第二章比较详细地讨论了这一关键性课题。其余的章节是在射频电路设计中最需要的基本知识，包括：什么是射频电路的基本参数？为什么目前在射频和射频集成电路设计中出现从单端转化为差分结构的趋势？射频集成电路设计的主要难题是什么？如何克服这些障碍？ 在射频电路设计中，射频电路单元性能的好坏往往取决于射频接地的成功与否。射频电路的误差分析则关系到产品合格率，而产品合格率是一间公司的生命线。《射频电路和射频集成电路设计中的关键课题》有两个特色。首先，在已出版了的大多数射频电路和射频集成电路设计的书中，其內容是讨论一个个射频电路单元，譬如，低噪声放大器，混频器，功率放大器， 压控振蕩器，頻率综合器。因此，可以把它们归类为纵向论述的书。《射频电路和射频集成电路设计中的关键课题》则不是讨论一个个射频电路单元， 而是着重论述和強调在射频电路和射集成电路设计中共同的关键性课题，因此，这是一本橫向论述的书。其次，尽管有些内容是引自出版了的书刊和文献。在本讲座中不少内容是引自《射频电路和射频集成电路设计中的关键课题》作者的设计和工作报告。《射频电路和射频集成电路设计中的关键课题》可作为以下读者在射频电路和射频集成电路的设计，研究和学习中的参考书：射频电路和射频集成电路设计工程师，测试工程师，系统工程师和经理；射频电路和射频集成电路的有关研究人员；射频电路和射频集成电路有关专业的大学本科生，研究生和教授。
作者简介
Richard Chi-Hsi Li，male， was born in NanAn，QuanZhou ，Fujian，China .He graduated in the Physics Department of FuDan Unversity，Shanghai，China in 1985.From 1958 to 1973 .he and been working for the Institute of Geophysics ，Chineseacademy and the University of China Science and Technology，Beijing， China.
目录
Chapter 1 Importance of Impedance Matching 17
1.1 Difference between RF and Digital Circuit Design 17
1.1.1 Case # 1: Digital Circuits at Low Data Rate 18
1.1.2 Case # 2: Digital Circuits at High Data Rate 21
1.2 Significance of Impedance Matching 23
1.2.1 Power Transportation from a Source to a Load 23
1.2.2 Maximizing of Power Transportation without Phase Shift 24
1.2.3 Conjugate Impedance Matching and Voltage Reflection Coefficient 26
1.2.4 Impedance Matching Network 27
1.3 Problems due to Unmatched Status of Impedance 30
1.3.1 General Expression of Power Transportation 30
1.3.2 Power Instability and Additional Power Loss 33
1.3.3 Additional Distortion and Quasi-Noise 35
1.3.4 Power Measurement 38
1.3.5 Power Transportation and Voltage Transportation 40
1.3.6 Burning of a Transistor 44
References 45
Chapter 2 Impedance Matching 46
2.1 Impedance Measured by Small Signal 46
2.1.1 Impedance Measured by S Parameter Measurement 46
2.1.2 The Smith Chart: Impedance and Admittance Coordination 47
2.1.3 Accuracy of Smith Chart 51
2.1.4 Relationship between the Impedance in Series and in Parallel 52
2.2 Impedance Measured by Large Signal 55
2.3 Impedance Matching 58
2.3.1 One Part Matching Network 58
2.3.2 Recognition of Regions in a Smith Chart 60
2.3.3 Two Parts Matching Network 61
2.3.4 Two Parts Upward and Downward Impedance Transformer 71
2.3.5 Three Parts Matching Network and Impedance Transformer 75
2.3.5.1 Topology Limitation of Two Parts Matching Network 75
2.3.5.2 Π Type Matching Network 77
2.3.5.3 T Type Matching Network 83
2.4 Some Useful Schemes for Impedance Matching 89
2.4.1 Designs and Tests when ZL is not 50 Ω 89
2.4.2 Conversion between “T” and “Π” Type Matching Network 90
2.4.3 Parts in a Matching Network 92
2.4.4 Impedance Matching between Power Transportation Units 93
2.4.5 Impedance Matching for a Mixer 94
References 95
Chapter 3 RF Grounding 97
3.1 A True Story 97
3.2 Three Components for RF Grounding 99
3.2.1 “Zero” Capacitors 99
3.2.2 Micro Strip Line 103
3.2.3 RF Cable 108
3.3 Examples of RF grounding 110
3.3.1 Test PCB 110
3.3.1.1 Small Test PCB 111
3.3.1.1.1 Basic Types of Test PCB 111
3.3.1.1.2 RF Grounding with a Rectangular Metallic Frame 115
3.3.1.1.3 An Example 116
3.3.1.2 Large Test PCB 119
3.3.1.2.1 RF Grounding by “Zero” Chip Capacitors 119
3.3.1.2.2 RF Grounding by a Runner or a Cable
with Half or Quarter Wavelength 121
3.3.2 Isolation between Input and Output in a Mixer or an Up-converter 124
3.3.3 Calibration for Network Analyzer 125
3.4 RF Grounding for Reduction of Return Current Coupling 127
3.4.1 A Circuit Built by Discrete Parts on a PCB 127
3.4.2 RFICs 130
References 134
Chapter 4 Equivalent Circuits of Passive Chip Parts 135
4.1 Modeling of Passive Chip Parts 136
4.2 Characterizing of Passive Chip Parts by Network Analyzer 138
4.3 Extraction from the Measurement by Network Analyzer 140
4.3.1 Chip Capacitor 140
4.3.2 Chip Inductor 145
4.3.3 Chip Resistor 151
4. 4 Summary 154
References 155
Chapter 5 Single-ended Stage and Differential Pair 156
5.1 Basic Single-ended Stage 156
5.1.1 General Description 156
5.1.2 Small Signal Model of a Bipolar Transistor 158
5.1.2.1 Impedance of a CE (Common Emitter) Device 160
5.1.2.2 Impedance of a CB (Common Base) Device 162
5.1.2.3 Impedance of a CC (Common Collector) Device 165
5.1.2.4 Comparison between CE, CB, and CC Device 167
5.1.3 Small Signal Model of a MOSFET 168
5.1.3.1 Impedance of a CS (Common source) Device 171
5.1.3.2 Impedance of a CG (Common gate) Device 173
5.1.3.3 Impedance of a CD (Common drain) Device 174
5.1.3.4 Comparison between CS, CG, and CD Device 174
5.2 Differential pair 176
5.2.1 DC Transfer Characteristic 176
5.2.1.1 DC Transfer Characteristic of a Bipolar Differential Pair 176
5.2.1.2 DC Transfer Characteristic of a CMOS Differential Pair 178
5.2.2 Small Signal Characteristic 179
5.2.3 Improvement of CMRR 187
5.2.4 Increase of Voltage Swing 189
5.2.5 Cancellation of Interference 190
5.2.6 Noise in a Differential Pair 192
5.3 Apparent Difference between Single-ended Stage and
Differential pair 197
5.4 DC Offset 200
5.4.1 DC Offset in a Single-ended Device 200
5.4.2 Zero DC Offset in a Pseudo-Differential Pair 202
5.4.3 Why “Zero” IF or Direct Conversion 204
5.4.4 DC Offset Cancellation 206
5.4.4.1 “Chopping” Mixer 206
5.4.4.2 DC Offset Calibration 212
5.4.4.3 Hardware Schemes 213
References 215
Chapter 6 Balun 217
6.1 Coaxial Cable Balun 217
6.2 Ring Micro Strip Line Balun 219
6.3 Transformer Balun 222
6.4 Transformer Balun Composed by Two
Stacked 2x2 Transformers 225
6.5 LC Balun 229
References 238
Chapter 7 Tolerance Analysis 239
7.1 Importance of Tolerance Analysis 239
7.2 Fundamentals of Tolerance Analysis 241
7.2.1 Tolerance and Normal Distribution 241
7.2.2 6σ, Cp, and Cpk 246
7.2.3 Yield Rate and DPU 250
7.2.4 Poisson Distribution 253
7.3 Approach to 6σ Design and Production 254
7.4 An Example: Tunable Filter Design 259
7.4.1 Description of the Tunable Filter Design 260
7.4.2 Monte-Carlo Analysis 261
7.5 Appendix: Table of the Normal Distribution 267
References 268
Chapter 8 Prospect of RFIC Design 269
8.1 History of RFIC development 269
8.2 Isolation between Blocks in an RFIC 272
8.2.1 Definition and Measurement of Isolation 272
8.2.2 Isolation Technology 273
8.3 Low Q Value of Spiral Inductor 288
8.3.1 Skin Effect 289
8.3.2 Attenuation due to Substrate 290
8.3.3 Flux Leakage 291
8.3.4 Flux Cancellation 293
8.3.5 A Possible Solution --- Negative Resistance Compensation 294
8.3.5.1 Negative Resistance Generator with a FET 298
8.3.5.2 Negative Resistance Generator with Transformer 299
8.4 Layout 300
8.4.1 Runners 300
8.4.2 Parts 306
8.4.3 Variable Parts in RFIC 308
8.4.4 Symmetry 310
8.4.5 Via 311
8.4.6 Free Space on the Die 312
8.5 Two Challenges in an RFIC or SOC Design 313
8.5.1 Isolation 313
8.5.2 High Q Inductor for IC 314
References 315
Chapter 9 Noise, Gain, and Sensitivity of a Receiver 317
9.1 Noise in a Circuit Block or a System 317
9.1.1 Noise Sources 317
9.1.1.1 Shot Noise 317
9.1.1.2 Thermal Noise 318
9.1.1.3 Flicker Noise (1/f Noise) 319
9.1.2 Definition of Noise Figure 320
9.1.3 Noise Figure in a Noisy Two Port Block 321
9.1.4 Minimum Noise Figure and Equivalent Noise Resistor 326
9.1.4.1 Noise in a MOSFET 326
9.1.4.2 Noise in a Bipolar Device 327
9.2 Gain 330
9.2.1 Definition of Power Gains 330
9.2.2 Power Gain and Voltage Gain 334
9.3 Sensitivity 335
9.3.1 Standard Noise Source 335
9.3.2 Equivalent Input Noise 336
9.3.3 Sensitivity of a Receiver 336
References 338
Chapter 10 Non-linearity and Spurious Products 339
10.1 Spurious products 339
10.1.1 Harmonics 339
10.1.2 Complicated Spurious Products 341
10.2 IP (Intercept Point) and IMR (Inter-Modulation Rejection) 344
10.3 3rd order Intercept Point and Spurious Product 347
10.4 1 dB Compression Point and IP3 351
10.5 2nd Order Intercept Point and Spurious Product 353
10.6 Distortion 355
References 356
Chapter 11 Cascaded Equations and System Analysis 358
11.1 Cascaded Equation for Power Gain 358
11.2 Cascaded Equation for Noise Figure 361
11.3 Cascaded Equation for Intercept Point 364
11.4 Application of Cascaded Equations in the System Analysis 373
References 375
Chapter 12 From Analog to Digital Communication System 376
12.1 Modulation in an Analog Communication System 376
12.2 Encoding in a Digital Communication System 381
12.2.1 NRZ (Non-Return to Zero) and Manchester Format 381
12.2.2 BPSK (Binary Phase Shift Keying) 383
12.2.3 QPSK (Quadrature Phase Shift Keying), OQPSK, MSK 385
12.2.4 FSK (Frequency Shift Keying), CPFSK 389
12.3 Decoding and Bit-Error Probability 390
12.4 Error Correction Schemes 393
References 396
1.1 Difference between RF and Digital Circuit Design 17
1.1.1 Case # 1: Digital Circuits at Low Data Rate 18
1.1.2 Case # 2: Digital Circuits at High Data Rate 21
1.2 Significance of Impedance Matching 23
1.2.1 Power Transportation from a Source to a Load 23
1.2.2 Maximizing of Power Transportation without Phase Shift 24
1.2.3 Conjugate Impedance Matching and Voltage Reflection Coefficient 26
1.2.4 Impedance Matching Network 27
1.3 Problems due to Unmatched Status of Impedance 30
1.3.1 General Expression of Power Transportation 30
1.3.2 Power Instability and Additional Power Loss 33
1.3.3 Additional Distortion and Quasi-Noise 35
1.3.4 Power Measurement 38
1.3.5 Power Transportation and Voltage Transportation 40
1.3.6 Burning of a Transistor 44
References 45
Chapter 2 Impedance Matching 46
2.1 Impedance Measured by Small Signal 46
2.1.1 Impedance Measured by S Parameter Measurement 46
2.1.2 The Smith Chart: Impedance and Admittance Coordination 47
2.1.3 Accuracy of Smith Chart 51
2.1.4 Relationship between the Impedance in Series and in Parallel 52
2.2 Impedance Measured by Large Signal 55
2.3 Impedance Matching 58
2.3.1 One Part Matching Network 58
2.3.2 Recognition of Regions in a Smith Chart 60
2.3.3 Two Parts Matching Network 61
2.3.4 Two Parts Upward and Downward Impedance Transformer 71
2.3.5 Three Parts Matching Network and Impedance Transformer 75
2.3.5.1 Topology Limitation of Two Parts Matching Network 75
2.3.5.2 Π Type Matching Network 77
2.3.5.3 T Type Matching Network 83
2.4 Some Useful Schemes for Impedance Matching 89
2.4.1 Designs and Tests when ZL is not 50 Ω 89
2.4.2 Conversion between “T” and “Π” Type Matching Network 90
2.4.3 Parts in a Matching Network 92
2.4.4 Impedance Matching between Power Transportation Units 93
2.4.5 Impedance Matching for a Mixer 94
References 95
Chapter 3 RF Grounding 97
3.1 A True Story 97
3.2 Three Components for RF Grounding 99
3.2.1 “Zero” Capacitors 99
3.2.2 Micro Strip Line 103
3.2.3 RF Cable 108
3.3 Examples of RF grounding 110
3.3.1 Test PCB 110
3.3.1.1 Small Test PCB 111
3.3.1.1.1 Basic Types of Test PCB 111
3.3.1.1.2 RF Grounding with a Rectangular Metallic Frame 115
3.3.1.1.3 An Example 116
3.3.1.2 Large Test PCB 119
3.3.1.2.1 RF Grounding by “Zero” Chip Capacitors 119
3.3.1.2.2 RF Grounding by a Runner or a Cable
with Half or Quarter Wavelength 121
3.3.2 Isolation between Input and Output in a Mixer or an Up-converter 124
3.3.3 Calibration for Network Analyzer 125
3.4 RF Grounding for Reduction of Return Current Coupling 127
3.4.1 A Circuit Built by Discrete Parts on a PCB 127
3.4.2 RFICs 130
References 134
Chapter 4 Equivalent Circuits of Passive Chip Parts 135
4.1 Modeling of Passive Chip Parts 136
4.2 Characterizing of Passive Chip Parts by Network Analyzer 138
4.3 Extraction from the Measurement by Network Analyzer 140
4.3.1 Chip Capacitor 140
4.3.2 Chip Inductor 145
4.3.3 Chip Resistor 151
4. 4 Summary 154
References 155
Chapter 5 Single-ended Stage and Differential Pair 156
5.1 Basic Single-ended Stage 156
5.1.1 General Description 156
5.1.2 Small Signal Model of a Bipolar Transistor 158
5.1.2.1 Impedance of a CE (Common Emitter) Device 160
5.1.2.2 Impedance of a CB (Common Base) Device 162
5.1.2.3 Impedance of a CC (Common Collector) Device 165
5.1.2.4 Comparison between CE, CB, and CC Device 167
5.1.3 Small Signal Model of a MOSFET 168
5.1.3.1 Impedance of a CS (Common source) Device 171
5.1.3.2 Impedance of a CG (Common gate) Device 173
5.1.3.3 Impedance of a CD (Common drain) Device 174
5.1.3.4 Comparison between CS, CG, and CD Device 174
5.2 Differential pair 176
5.2.1 DC Transfer Characteristic 176
5.2.1.1 DC Transfer Characteristic of a Bipolar Differential Pair 176
5.2.1.2 DC Transfer Characteristic of a CMOS Differential Pair 178
5.2.2 Small Signal Characteristic 179
5.2.3 Improvement of CMRR 187
5.2.4 Increase of Voltage Swing 189
5.2.5 Cancellation of Interference 190
5.2.6 Noise in a Differential Pair 192
5.3 Apparent Difference between Single-ended Stage and
Differential pair 197
5.4 DC Offset 200
5.4.1 DC Offset in a Single-ended Device 200
5.4.2 Zero DC Offset in a Pseudo-Differential Pair 202
5.4.3 Why “Zero” IF or Direct Conversion 204
5.4.4 DC Offset Cancellation 206
5.4.4.1 “Chopping” Mixer 206
5.4.4.2 DC Offset Calibration 212
5.4.4.3 Hardware Schemes 213
References 215
Chapter 6 Balun 217
6.1 Coaxial Cable Balun 217
6.2 Ring Micro Strip Line Balun 219
6.3 Transformer Balun 222
6.4 Transformer Balun Composed by Two
Stacked 2x2 Transformers 225
6.5 LC Balun 229
References 238
Chapter 7 Tolerance Analysis 239
7.1 Importance of Tolerance Analysis 239
7.2 Fundamentals of Tolerance Analysis 241
7.2.1 Tolerance and Normal Distribution 241
7.2.2 6σ, Cp, and Cpk 246
7.2.3 Yield Rate and DPU 250
7.2.4 Poisson Distribution 253
7.3 Approach to 6σ Design and Production 254
7.4 An Example: Tunable Filter Design 259
7.4.1 Description of the Tunable Filter Design 260
7.4.2 Monte-Carlo Analysis 261
7.5 Appendix: Table of the Normal Distribution 267
References 268
Chapter 8 Prospect of RFIC Design 269
8.1 History of RFIC development 269
8.2 Isolation between Blocks in an RFIC 272
8.2.1 Definition and Measurement of Isolation 272
8.2.2 Isolation Technology 273
8.3 Low Q Value of Spiral Inductor 288
8.3.1 Skin Effect 289
8.3.2 Attenuation due to Substrate 290
8.3.3 Flux Leakage 291
8.3.4 Flux Cancellation 293
8.3.5 A Possible Solution --- Negative Resistance Compensation 294
8.3.5.1 Negative Resistance Generator with a FET 298
8.3.5.2 Negative Resistance Generator with Transformer 299
8.4 Layout 300
8.4.1 Runners 300
8.4.2 Parts 306
8.4.3 Variable Parts in RFIC 308
8.4.4 Symmetry 310
8.4.5 Via 311
8.4.6 Free Space on the Die 312
8.5 Two Challenges in an RFIC or SOC Design 313
8.5.1 Isolation 313
8.5.2 High Q Inductor for IC 314
References 315
Chapter 9 Noise, Gain, and Sensitivity of a Receiver 317
9.1 Noise in a Circuit Block or a System 317
9.1.1 Noise Sources 317
9.1.1.1 Shot Noise 317
9.1.1.2 Thermal Noise 318
9.1.1.3 Flicker Noise (1/f Noise) 319
9.1.2 Definition of Noise Figure 320
9.1.3 Noise Figure in a Noisy Two Port Block 321
9.1.4 Minimum Noise Figure and Equivalent Noise Resistor 326
9.1.4.1 Noise in a MOSFET 326
9.1.4.2 Noise in a Bipolar Device 327
9.2 Gain 330
9.2.1 Definition of Power Gains 330
9.2.2 Power Gain and Voltage Gain 334
9.3 Sensitivity 335
9.3.1 Standard Noise Source 335
9.3.2 Equivalent Input Noise 336
9.3.3 Sensitivity of a Receiver 336
References 338
Chapter 10 Non-linearity and Spurious Products 339
10.1 Spurious products 339
10.1.1 Harmonics 339
10.1.2 Complicated Spurious Products 341
10.2 IP (Intercept Point) and IMR (Inter-Modulation Rejection) 344
10.3 3rd order Intercept Point and Spurious Product 347
10.4 1 dB Compression Point and IP3 351
10.5 2nd Order Intercept Point and Spurious Product 353
10.6 Distortion 355
References 356
Chapter 11 Cascaded Equations and System Analysis 358
11.1 Cascaded Equation for Power Gain 358
11.2 Cascaded Equation for Noise Figure 361
11.3 Cascaded Equation for Intercept Point 364
11.4 Application of Cascaded Equations in the System Analysis 373
References 375
Chapter 12 From Analog to Digital Communication System 376
12.1 Modulation in an Analog Communication System 376
12.2 Encoding in a Digital Communication System 381
12.2.1 NRZ (Non-Return to Zero) and Manchester Format 381
12.2.2 BPSK (Binary Phase Shift Keying) 383
12.2.3 QPSK (Quadrature Phase Shift Keying), OQPSK, MSK 385
12.2.4 FSK (Frequency Shift Keying), CPFSK 389
12.3 Decoding and Bit-Error Probability 390
12.4 Error Correction Schemes 393
References 396
猜您喜欢
