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计算机体系结构习题与解答（英文版）
作者：美.卡特著
出版社：机械工业出版社
出版时间：2002-08-01
ISBN：9787111104186
定价：¥30.00
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内容简介
《计算机体系结构习题与解答》全美经典学习指导系列是一套快捷有效的学习指南，该套丛书针对各专业的技术重点提供了数百个实例、习题及答案。通过这些实战练习，不但可以洞悉各门技术精髓，而且能够使考试成绩大幅攀升，更会助你与国外大学生的计算机水平看齐，为将来考研或出国深造奠定坚实基础。全美经典学习指导系列深得高校学生的喜爱。由于有了这套丛书，在历年的专业考试中，成千上万的学生获得了优异成绩。想成为一名优等生吗？——请选择全美经典学习指导系列！如果时间不裕却想成绩骄人，这本书可以助你：●通过具体范例解决疑难问题●考前快速强化●迅速找到答案●快捷而高效地学习●迅速掌握技术重点，无需翻阅冗长的教科书全美经典学习指导系列以方便快捷的形式提供了考生需要了解的信息，同时不致使你淹没在不必要的细节当中。另外，还可以通过大量的编程练习来测试所学的技巧。该丛书可以与任何教材配合使用，使学生们能够根据各自的进度来学习，从而获得事半功倍的效果！全美经典学习指导系列的内容系统而完备，是毕业考试和专业考试的理想参考书。本书内容包括：●计算机系统中软硬件设计要素概述●软硬件接口的简要解释●有效利用系统资源的完整细节●有关指令集、流水线、高速缓冲存储器、存储器、I／O等方面的192个习题与解答如果想获得优异成绩并且全面掌握计算机体系结构，本书是不可或缺的最佳辅导老师。本书介绍了与计算机体系结构相关的各种主题。第1章到第5章介绍了计算机体系结构课程中的许多基本概念，包括：数据表示与算术运算、计算机组织、编程模型、处理器设计。第6章和第7章分别讨论了流水线和指令级并行性方法，它们都是影响现代处理器的重要因素。第8章到第10章介绍了各种存储器系统的设计，包括存储器层次结构、高速缓冲存储器和虚拟存储器。第11章讨论了输入／输出系统。第12章介绍了多处理器系统。通过阅读本书，读者能够迅速了解与计算机体系结构相关的各种知识，并将其应用到其他课程的学习和编程实践中。本书内容全面，每章均提供了大量的实例和习题，是学习计算机体系结构课程的一本极佳教辅材料。
作者简介
暂缺《计算机体系结构习题与解答（英文版）》作者简介
目录
CHAPTER 1 Introd uction
1.1 Purpose of This Book
1.2 Background Assumed
1.3 Material Covered
1.4 Chapter Objectives
1.5 Technological Trends
1.6 Measuring Performance
1.7 Speedup
1.8 Amdahl's Law
1.9 S
Solved Problems
CHAPTER 2 Data Representations and Computer Arithmetic
2.1 Objectives
2.2 From Electrons to Bits
2.3 Binary Representation of Positive Integers
2.4 Arithmetic Operations on Positive Integers
2.5 Negative Integers
2.6 Floating-Point Numbers
2.7 S
Solved Problems
CHAPTER 3 Computer Organization
3.1 Objectives
3.2 Introduction
3.3 Programs
3.4 Operating Systems
3.5 Computer Oganization
3.6 Summary
Solved Problems
CHAPTER 4 Programming Models
4.1 Objectives
4.2 Introduction
4.3 Types of Instructions
4.4 Stack-Based Architectures
4.5 General-Purpose Register Architectures
4.6 Comparing Stack-Based and General-Purpose Register
Architectures
4.7 Using Stacks to Implement Procedure Calls
4.8 Summary '
Solved Problems
CHAPTER 5 Processor Design
5.1 Objectives
5.2 Introduction
5.3 Instruction Set Architecture
5.4 Processor Microarchitecture
5.5 S
Solved Problems
CHAPTER 6 Pipelining
6.1 Objectives
6.2 Introduction
6.3 Pipelining
6.4 Instruction Hazards and Their Impact on Throughput
6.5 Predicting Execution Time in Pipelined Processors
6.6 Result Forwarding (Bypassing)
6.7 S
Solved Problems
CHAPTER 7 Instruction-Level Parallelism
7.1 Objectives
7.2 Introduction.
7.3 What is Instruction-Level Parallelism?
7.4 Limitations of instruction-Level Parallelism
7.5 Superscalar Processors
7.6 In-Order versus Out-of-Order Execution
7.7 Register Renaming '
7.8 VLIW Processors
7.9 Compilation Techniques for Instruction-Level Palallelism
7.1O S
Solved Problems
CHAPTER 8 Memory Systems
8.1 Objectives
8.2 Introduction
8.3 Latency, Throughput and Bandwidth
8.4 Memory Hierarchies
8.5 Memory Technologies
8.6 S
Solved Problems
CHAPTER 9 Caches
9.1 Objectives
9.2 Introduction
9.3 Data Caches, Instruction Caches, and Unified Caches
9.4 Describing Caches
9.5 Capacity
9.6 Line Length
9.7 Associativity
9.8 Replacement Policy
9.9 Write-Back versus Write-Through Caches
9.1O Cache Implementations
9.11 Tag Arrays
9.12 Hit/Miss Logic
9.13 Data Arrays
9.14 Categorizing Cache Misses
9.15 Multilevel Caches
9.16 S
Solved Problems
CHAPTER IO Virtual Nemory
l0.1 Objectives '
10.2 Introduction
10.3 Address Translation
10.4 Demand Paging versus Swapping
10.5 Page Tables
10.6 Translation Lookaside Buffers
10.7 Proteaion
10.8 Caches and Virtual Memory
10.9 Summary
Solved Problems
CHAPTER 11 I/O
11.1 Objectives
11.2 Introduction
11.3 I/0 Buses
11.4 Interrupts
11.5 Memory-Mapped I/O
11.6 Direct Memory Aceess
11.7 I/O Devices
11.8 Disk Systems
11.9 S
Solved Problems
CHAPTER 12 Multiprocessors
12.1 Objectives
12.2 Introduction
12.3 Speedup and Performance
12.4 Multiprocessor Systems
12.5 Message-Passing Systems
12.6 Shared-Memory Systems
12.7 Comparing Message-Passing and Shared Memory
12.8 Summary
Solved Problems
INDEX
1.1 Purpose of This Book
1.2 Background Assumed
1.3 Material Covered
1.4 Chapter Objectives
1.5 Technological Trends
1.6 Measuring Performance
1.7 Speedup
1.8 Amdahl's Law
1.9 S
Solved Problems
CHAPTER 2 Data Representations and Computer Arithmetic
2.1 Objectives
2.2 From Electrons to Bits
2.3 Binary Representation of Positive Integers
2.4 Arithmetic Operations on Positive Integers
2.5 Negative Integers
2.6 Floating-Point Numbers
2.7 S
Solved Problems
CHAPTER 3 Computer Organization
3.1 Objectives
3.2 Introduction
3.3 Programs
3.4 Operating Systems
3.5 Computer Oganization
3.6 Summary
Solved Problems
CHAPTER 4 Programming Models
4.1 Objectives
4.2 Introduction
4.3 Types of Instructions
4.4 Stack-Based Architectures
4.5 General-Purpose Register Architectures
4.6 Comparing Stack-Based and General-Purpose Register
Architectures
4.7 Using Stacks to Implement Procedure Calls
4.8 Summary '
Solved Problems
CHAPTER 5 Processor Design
5.1 Objectives
5.2 Introduction
5.3 Instruction Set Architecture
5.4 Processor Microarchitecture
5.5 S
Solved Problems
CHAPTER 6 Pipelining
6.1 Objectives
6.2 Introduction
6.3 Pipelining
6.4 Instruction Hazards and Their Impact on Throughput
6.5 Predicting Execution Time in Pipelined Processors
6.6 Result Forwarding (Bypassing)
6.7 S
Solved Problems
CHAPTER 7 Instruction-Level Parallelism
7.1 Objectives
7.2 Introduction.
7.3 What is Instruction-Level Parallelism?
7.4 Limitations of instruction-Level Parallelism
7.5 Superscalar Processors
7.6 In-Order versus Out-of-Order Execution
7.7 Register Renaming '
7.8 VLIW Processors
7.9 Compilation Techniques for Instruction-Level Palallelism
7.1O S
Solved Problems
CHAPTER 8 Memory Systems
8.1 Objectives
8.2 Introduction
8.3 Latency, Throughput and Bandwidth
8.4 Memory Hierarchies
8.5 Memory Technologies
8.6 S
Solved Problems
CHAPTER 9 Caches
9.1 Objectives
9.2 Introduction
9.3 Data Caches, Instruction Caches, and Unified Caches
9.4 Describing Caches
9.5 Capacity
9.6 Line Length
9.7 Associativity
9.8 Replacement Policy
9.9 Write-Back versus Write-Through Caches
9.1O Cache Implementations
9.11 Tag Arrays
9.12 Hit/Miss Logic
9.13 Data Arrays
9.14 Categorizing Cache Misses
9.15 Multilevel Caches
9.16 S
Solved Problems
CHAPTER IO Virtual Nemory
l0.1 Objectives '
10.2 Introduction
10.3 Address Translation
10.4 Demand Paging versus Swapping
10.5 Page Tables
10.6 Translation Lookaside Buffers
10.7 Proteaion
10.8 Caches and Virtual Memory
10.9 Summary
Solved Problems
CHAPTER 11 I/O
11.1 Objectives
11.2 Introduction
11.3 I/0 Buses
11.4 Interrupts
11.5 Memory-Mapped I/O
11.6 Direct Memory Aceess
11.7 I/O Devices
11.8 Disk Systems
11.9 S
Solved Problems
CHAPTER 12 Multiprocessors
12.1 Objectives
12.2 Introduction
12.3 Speedup and Performance
12.4 Multiprocessor Systems
12.5 Message-Passing Systems
12.6 Shared-Memory Systems
12.7 Comparing Message-Passing and Shared Memory
12.8 Summary
Solved Problems
INDEX
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