书籍详情
VLSI数字信号处理系统设计与实现（英文版）
作者：（美）帕赫 著
出版社：机械工业出版社
出版时间：2003-10-01
ISBN：9787111123484
定价：¥79.00
购买这本书可以去
内容简介
视频压缩，无线通信，全球定位、雷达影像……在DSP的广泛应用领域内，怎样设计出高速、精巧的VLSI系统？并行处理、流水线。ASIC、可编程数字信号处理器，为实现DSP算法，技术与工具怎样结合才能更加完美？本书将为您提供答案。它既是折叠、异步流水线等技术的资源宝库，同时也是方向标，通过大量的实践经验指明了进入VLSI王国的捷径。本书特点：通过上百张图片对不同的DSP算法进行解释每章后的习题将技术与现实紧密结合起来适用面广，可作为《VlSI数字信号处理体系结构》或《高性能VLSI系统设计》等课程的教材提供有无线。有线。多媒体通信多个领域内的技术与经验作者简介：KeshabK．Parhi于印度理工学院获得工学学士学位；1984年于宾夕法尼亚大学获得电子与电气工程硕士学位：1988年在加利福尼亚大学伯克利分校获得博士学位。自1988年以来，一直执教于明尼苏达大学电子和计算机工程系，最近刚刚获得McKnight大学杰出教授荣誉称号。他的研究方向包括：并发算法，通信架构设计、信号和图像处理系统。数字集成电路、VLSI数字滤波器等。他是IEEE成员。作为主席，他主持了IEEE1995VLSI数字处理研讨会。IEEE1996特殊应用系统、体系结构和处理器研讨会以及IEEE2002数字处理的设计与实现研讨会。
作者简介
KeshabK.Parhi于印度理工学院获得工学学士学位：1984年于宾夕法尼亚大学获得电子工程硕士学位：1988年在加利福尼亚大学伯克利分校获得博士学位。自1988年以来，一直执教于昆尼苏达大学电子和计算机工程系，最近刚刚获得McKnight大学杰出教授荣誉称号。他的研究方向包括：并发算法、通信架构设计、信号和图像处理系统、数字集成电路、VLSI数字滤波器等。他是IEEE成员。作为主席，他主持了IEEE1995VLSI数字处理研讨会、IEEE1996特殊应用系统、体系结构和处理器研讨会以及IEEE2002数字处理的设计与实现研讨会。
目录
Preface
Introduction to Digital Signal Processing Systems
1.1 Introduction
1.2 Typical DSP Algorithms
1.3 DSP Application Demands and Scaled CMOS Technologies
1.4 Representations of DSP Algorithms
1.5 Book Outline
References
2 Iteration Bound
2.1 Introduction
2.2 Data-Flow Graph Representations
2.3 Loop Bound and Iteration Bound
2.4 Algorithms for Computing Iteration Bound
2.5 Iteration Bound of Multirate Data-Flow Graphs
2.6 Conclusions
2.7 Problems
References
3 Pipelining and Parallel Processing
3.1 Introduction
3.2 Pipelining of FIR Digital Filters
3.3 Parallel Processing
3.4 Pipelining and Parallel Processing for Low Power
3.5 Conclusions
3.6 Problems
References
4 Retiming
4.1 Introduction
4.2 Definitions and Properties
4.3 Solving Systems of Inequalities
4.4 Retiming Techniques
4.5 Conclusions
4.6 Problems
References
5 Unfolding
5.1 Introduction
5.2 An Algorithm for Unfolding
5.3 Properties of Unfolding
5.4 Critical Path, Unfolding, and Retiming
5.5 Applications of Unfolding
5.6 Conclusions
5.7 Problems
References
6 Folding
6.1 Introduction
6.2 Folding Transformation
6.3 Register Minimization Techniques
6.4 Register Minimization in Folded Architectures
6.5 Folding of Multirate Systems
6.6 Conclusions
6.7 Problems
References
7 .Systolic Architecture Design
7.1 Introduction
7.2 Systolic Array Design Methodology
7.3 FIR Systolic Arrays
7.4 Selection of Scheduling Vector
7.5 Matrix-Matrix Multiplication and 2D Systolic Array Design
7.6 Systolic Design for Space Representations Containing Delays
7.7 Conclusions
7.8 Problems
References
8 Fast Convolution
8.1 Introduction
8.2 Cook-Toom Algorithm
8.3 Winograd Algorithm
8.4 Iterated Convolution
8.5 Cyclic Convolution
8.6 Design of Fast Convolution Algorithm by Inspection
8.7 Conclusions
8.8 Problems
References
9 Algorithmic Strength Reduction in Filters and Transforms
9.1 Introduction
9.2 Parallel FIR Filters
9.3 Discrete Cosine Transform and Inverse DCT
9.4 Parallel Architectures for Rank-Order Filters
9.5 Conclusions
9.6 Problems
References
10 Pipelined and Parallel Recursive and Adaptive Filters
10.1 Introduction
10.2 Pipeline Interleaving in Digital Filters
10.3 Pipelining in 1st-Order IIR Digital Filters
10.4 Pipelining in Higher-Order IIR Digital Filters
10.5 Parallel Processing for IIR filters
10.6 Combined Pipelining and Parallel Processing for IIR Filters
10.7 Low-Power IIR Filter Design Using Pipelining and Parallel Processing
10.8 Pipelined Adaptive Digital Filters
10.9 Conclusions
10.10 Problems
References
11 Scaling and Roundoff Noise
11.1 Introduction
11.2 Scaling and Roundoff Noise
11.3 State Variable Description of Digital Filters
11.4 Scaling and Roundoff Noise Computation
11.5 Roundoff Noise in Pipelined IIR Filters
11.6 Roundoff Noise Computation Using State Variable Description
11.7 Slow-Down, Retiming, and Pipelining
11.8 Conclusions
11.9 Problems
References
12 Digital Lattice Filter Structures
12.1 Introduction
12.2 Schur Algorithm
12.3 Digital Basic Lattice Filters
12.4 Derivation of One-Multiplier Lattice Filter
12.5 Derivation of Normalized Lattice Filter
12.6 Derivation of Scaled-Normalized Lattice Filter
12.7 Roundoff Noise Calculation in Lattice Filters
12.8 Pipelining of Lattice IIR Digital Filters
12.9 Design Examples of Pipelined Lattice Filters
12.10 Low-Power CMOS Lattice IIR Filters
12.11 Conclusions
12.12 Problems
References
13 Bit-Level Arithmetic Architectures
13.1 Introduction
13.2 Parallel Multipliers
13.3 Interleaved Floor-plan and Bit-Plane-Based Digital Filters
13.4 Bit-Serial Multipliers
13.5 Bit-Serial Filter Design and Implementation
13.6 Canonic Signed Digit Arithmetic
13.7 Distributed Arithmetic
13.8 Conclusions
13.9 Problems
References
14 Redundant Arithmetic
14.1 Introduction
14.2 Redundant Number Representations
14.3 Carry-Free Radix-2 Addition and Subtraction
14.4 Hybrid Radix-4 Addition
14.5 Radix-2 Hybrid Redundant Multiplication Architectures
14.6 Data Format Conversion
14.7 Redundant to Nonredundant Converter
14.8 Conclusions
14.9 Problems
References
15 Numerical Strength Reduction
15.1 Introduction
15.2 Subexpression Elimination
15.3 Multiple Constant Multiplication
15.4 Subexpression Sharing in Digital Filters
15.5 Additive and Multiplicative Number Splitting
15.6 Conclusions
15.7 Problems
References
16 Synchronous, Wave, and Asynchronous Pipelines
16.1 Introduction
16.2 Synchronous Pipelining and Clocking Styles
16.3 Clock Skew and Clock Distribution in Bit-Level Pipelined VLSI Designs
16.4 Wave Pipelining
16.5 Constraint Space Diagram and Degree of Wave Pipelining
16.6 Implementation of Wave-Pipelined Systems
16.7 Asynchronous Pipelining
16.8 Signal Transition Graphs
16.9 Use of STG to Design Interconnection Circuits
16.10 Implementation of Computational Units
16.11 Conclusions
16.12 Problems
References
17 Low-Power Design
17.1 Introduction
17.2 Theoretical Background
17.3 Scaling Versus Power Consumption
17.4 Power Analysis
17.5 Power Reduction Techniques
17.6 Power Estimation Approaches
17.7 Conclusions
17.8 Problems
References
18 Programmable Digital Signal Processors
18.1 Introduction
18.2 Evolution of Programmable Digital Signal Processors
18.3 Important Features of DSP Processors
18.4 DSP Processors for Mobile and Wireless Communications
18.5 Processors for Multimedia Signal Processing
18.6 Conclusions
References
Appendix A: Shortest Path Algorithms
A.1 Introduction
A.2 The Bellman-Ford Algorithm
A.3 The Floyd-Warshall Algorithm
A.4 Computational Complexities
References
Appendix B: Scheduling and Allocation Techniques
B.1 Introduction
B.2 Iterative/Constructive Scheduling Algorithms
B.3 Transformational Scheduling Algorithms
B.4 Integer Linear Programming Models
Appendix C: Euclidean GCD Algorithm
C.1 Introduction
C.2 Euclidean GCD Algorithm for Integers
C.3 Euclidean GCD Algorithm for Polynomials
Appendix D: Orthonormality of Schur Polynomials
D.1 Orthogonality of Schur Polynomials
D.2 Orthonormality of Schur Polynomials
Appendix E: Fast Binary Adders and Multipliers
E.1 Introduction
E.2 Multiplexer-Based Fast Binary Adders
E.3 Wallace Tree and Dadda Multiplier
References
Appendix F: Scheduling in Bit-Serial Systems
F.1 Introduction
F.2 Outline of the Scheduling Algorithm
F.3 Minimum Cost Solution
F.4 Scheduling of Edges with Delays
References
Appendix G: Coefficient Quantization in FIR Filters
G.1 Introduction
G.2 NUS Quantization Algorithm
References
Index
Introduction to Digital Signal Processing Systems
1.1 Introduction
1.2 Typical DSP Algorithms
1.3 DSP Application Demands and Scaled CMOS Technologies
1.4 Representations of DSP Algorithms
1.5 Book Outline
References
2 Iteration Bound
2.1 Introduction
2.2 Data-Flow Graph Representations
2.3 Loop Bound and Iteration Bound
2.4 Algorithms for Computing Iteration Bound
2.5 Iteration Bound of Multirate Data-Flow Graphs
2.6 Conclusions
2.7 Problems
References
3 Pipelining and Parallel Processing
3.1 Introduction
3.2 Pipelining of FIR Digital Filters
3.3 Parallel Processing
3.4 Pipelining and Parallel Processing for Low Power
3.5 Conclusions
3.6 Problems
References
4 Retiming
4.1 Introduction
4.2 Definitions and Properties
4.3 Solving Systems of Inequalities
4.4 Retiming Techniques
4.5 Conclusions
4.6 Problems
References
5 Unfolding
5.1 Introduction
5.2 An Algorithm for Unfolding
5.3 Properties of Unfolding
5.4 Critical Path, Unfolding, and Retiming
5.5 Applications of Unfolding
5.6 Conclusions
5.7 Problems
References
6 Folding
6.1 Introduction
6.2 Folding Transformation
6.3 Register Minimization Techniques
6.4 Register Minimization in Folded Architectures
6.5 Folding of Multirate Systems
6.6 Conclusions
6.7 Problems
References
7 .Systolic Architecture Design
7.1 Introduction
7.2 Systolic Array Design Methodology
7.3 FIR Systolic Arrays
7.4 Selection of Scheduling Vector
7.5 Matrix-Matrix Multiplication and 2D Systolic Array Design
7.6 Systolic Design for Space Representations Containing Delays
7.7 Conclusions
7.8 Problems
References
8 Fast Convolution
8.1 Introduction
8.2 Cook-Toom Algorithm
8.3 Winograd Algorithm
8.4 Iterated Convolution
8.5 Cyclic Convolution
8.6 Design of Fast Convolution Algorithm by Inspection
8.7 Conclusions
8.8 Problems
References
9 Algorithmic Strength Reduction in Filters and Transforms
9.1 Introduction
9.2 Parallel FIR Filters
9.3 Discrete Cosine Transform and Inverse DCT
9.4 Parallel Architectures for Rank-Order Filters
9.5 Conclusions
9.6 Problems
References
10 Pipelined and Parallel Recursive and Adaptive Filters
10.1 Introduction
10.2 Pipeline Interleaving in Digital Filters
10.3 Pipelining in 1st-Order IIR Digital Filters
10.4 Pipelining in Higher-Order IIR Digital Filters
10.5 Parallel Processing for IIR filters
10.6 Combined Pipelining and Parallel Processing for IIR Filters
10.7 Low-Power IIR Filter Design Using Pipelining and Parallel Processing
10.8 Pipelined Adaptive Digital Filters
10.9 Conclusions
10.10 Problems
References
11 Scaling and Roundoff Noise
11.1 Introduction
11.2 Scaling and Roundoff Noise
11.3 State Variable Description of Digital Filters
11.4 Scaling and Roundoff Noise Computation
11.5 Roundoff Noise in Pipelined IIR Filters
11.6 Roundoff Noise Computation Using State Variable Description
11.7 Slow-Down, Retiming, and Pipelining
11.8 Conclusions
11.9 Problems
References
12 Digital Lattice Filter Structures
12.1 Introduction
12.2 Schur Algorithm
12.3 Digital Basic Lattice Filters
12.4 Derivation of One-Multiplier Lattice Filter
12.5 Derivation of Normalized Lattice Filter
12.6 Derivation of Scaled-Normalized Lattice Filter
12.7 Roundoff Noise Calculation in Lattice Filters
12.8 Pipelining of Lattice IIR Digital Filters
12.9 Design Examples of Pipelined Lattice Filters
12.10 Low-Power CMOS Lattice IIR Filters
12.11 Conclusions
12.12 Problems
References
13 Bit-Level Arithmetic Architectures
13.1 Introduction
13.2 Parallel Multipliers
13.3 Interleaved Floor-plan and Bit-Plane-Based Digital Filters
13.4 Bit-Serial Multipliers
13.5 Bit-Serial Filter Design and Implementation
13.6 Canonic Signed Digit Arithmetic
13.7 Distributed Arithmetic
13.8 Conclusions
13.9 Problems
References
14 Redundant Arithmetic
14.1 Introduction
14.2 Redundant Number Representations
14.3 Carry-Free Radix-2 Addition and Subtraction
14.4 Hybrid Radix-4 Addition
14.5 Radix-2 Hybrid Redundant Multiplication Architectures
14.6 Data Format Conversion
14.7 Redundant to Nonredundant Converter
14.8 Conclusions
14.9 Problems
References
15 Numerical Strength Reduction
15.1 Introduction
15.2 Subexpression Elimination
15.3 Multiple Constant Multiplication
15.4 Subexpression Sharing in Digital Filters
15.5 Additive and Multiplicative Number Splitting
15.6 Conclusions
15.7 Problems
References
16 Synchronous, Wave, and Asynchronous Pipelines
16.1 Introduction
16.2 Synchronous Pipelining and Clocking Styles
16.3 Clock Skew and Clock Distribution in Bit-Level Pipelined VLSI Designs
16.4 Wave Pipelining
16.5 Constraint Space Diagram and Degree of Wave Pipelining
16.6 Implementation of Wave-Pipelined Systems
16.7 Asynchronous Pipelining
16.8 Signal Transition Graphs
16.9 Use of STG to Design Interconnection Circuits
16.10 Implementation of Computational Units
16.11 Conclusions
16.12 Problems
References
17 Low-Power Design
17.1 Introduction
17.2 Theoretical Background
17.3 Scaling Versus Power Consumption
17.4 Power Analysis
17.5 Power Reduction Techniques
17.6 Power Estimation Approaches
17.7 Conclusions
17.8 Problems
References
18 Programmable Digital Signal Processors
18.1 Introduction
18.2 Evolution of Programmable Digital Signal Processors
18.3 Important Features of DSP Processors
18.4 DSP Processors for Mobile and Wireless Communications
18.5 Processors for Multimedia Signal Processing
18.6 Conclusions
References
Appendix A: Shortest Path Algorithms
A.1 Introduction
A.2 The Bellman-Ford Algorithm
A.3 The Floyd-Warshall Algorithm
A.4 Computational Complexities
References
Appendix B: Scheduling and Allocation Techniques
B.1 Introduction
B.2 Iterative/Constructive Scheduling Algorithms
B.3 Transformational Scheduling Algorithms
B.4 Integer Linear Programming Models
Appendix C: Euclidean GCD Algorithm
C.1 Introduction
C.2 Euclidean GCD Algorithm for Integers
C.3 Euclidean GCD Algorithm for Polynomials
Appendix D: Orthonormality of Schur Polynomials
D.1 Orthogonality of Schur Polynomials
D.2 Orthonormality of Schur Polynomials
Appendix E: Fast Binary Adders and Multipliers
E.1 Introduction
E.2 Multiplexer-Based Fast Binary Adders
E.3 Wallace Tree and Dadda Multiplier
References
Appendix F: Scheduling in Bit-Serial Systems
F.1 Introduction
F.2 Outline of the Scheduling Algorithm
F.3 Minimum Cost Solution
F.4 Scheduling of Edges with Delays
References
Appendix G: Coefficient Quantization in FIR Filters
G.1 Introduction
G.2 NUS Quantization Algorithm
References
Index
猜您喜欢
