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计算机系统体系结构（第3版 英文版）
作者：（美）[M.M.马尼奥]M.Morris Mano著
出版社：清华大学出版社
出版时间：1998-06-01
ISBN：9787302028314
定价：¥28.00
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内容简介
本书介绍计算机体系结构以及计算机组织与设计，向读者提供掌握计算机硬件操作所必需的基本知识。内容包括：用于计算机组织和设计的各种部件；设计一台计算机的详细步骤：中央处理机，输入/输出及存储器的组织与体系结构；多处理概念。全书分13章：1.数字逻辑电路，2.数字部件。3.数据表示法，4.寄存器传输与微操作，5.基本计算机组织与设计，6.基本计算机的程序设计，7.微程序控制，8.中央处理机，9.流水处理与向量处理，10.计算机体系结构，11.输入/输出组织，12.存储器组织，13.多处理机。本书可作电气工程，计算机工程或计算机科学系的“计算机硬件系统”课的教材，还可作工程技术及科研人员了解计算机硬件体系结构基本知识的自学参考书。
作者简介
暂缺《计算机系统体系结构（第3版 英文版）》作者简介
目录
Preface
CHAPTER ONE Digital Logic Circuits
1-1 Digital Computcrs
1-2 Logic Gates
Boolean Atgebra
1-3 Complement of a Fumction
Map Simplification
Product-of-Sums Simplification
1-4 Don't-Care Conditions
Combinational Circuits
1-5 Half-Adder
Full-Adder
1-6 Flip-Flops
SR Flip-Flop
DFlip-Flop
1-8 JK Flip-Flop
T Flip-Flop
Edge-TriggeredT Flip--Flops
Excitation Tables
Sequential Circuits
1-9 Flip-Flop input Equations
StateTable
State Diagram
Design Example
Design Procedure
Problems
CHAPTER TWO References
2-1 Integrated Cireuits
2-2 Decodeis
NAND Gate Decoder
Decoder Expansion
Encoders
2-3 Multiplewrs
2-4 Registcrs
register with Parallel Load
2-5 Shift Registers
Bidirectional Shift Register with Paraflel Load
2-6 Binary Counters
Binary Counter with Pa6rallel Load
2-7 Memory Unit
Random-Access Memory
Read-Only Memory
Types of ROMs
Problems
References
CHAPTER THREE Data Representation
DataTypcs
Number Systems
Octal and Hexadecimal Numbers
Dectmal Represention
Alphanumeric Representation
Complements
(r-l) Complement
(r's) Complement
Suberaction of Unsigned Numbers
Fixcd-Point Representation
Integer Represention
Arithonec Addition
Aruhmetic Subtraction
Ovverflow
Decimal Fixed-Pomt Representation
Floating-Point Representation
Other Binary Codes
GTay Code
Other Decimal Codes
Other Alphanumeric Codes
Error Detection Codes
Probkms
References
CHAPTER FOUR Register Transfer and Microoperations
Register Transfer Language
Register Transfer
Bus and Memory Transfers
Three-State Bus Buffers
Memory Transfer
Arithmetic Micrboperations
Binary Adder
Binary Adder-Subtactor
Binary Jncrementer
Arithmetic Circuit
Logic Microoperations
List of Logic Microoperations
Hardware ImpJementotion
Some Applications
Shift Microoperations
Hardware Implementation
Arithmetic Logic Shift Unit
Problems
References
CHAPTEK FIVE Basic Computer Organization and Design
Instruction Codes
Stored Program Organitaoon
indirect Address
Computer Registers
Common Bus System
Computer Instructions
Imtrucrion Set Completeness
Tuning and Control
Inscruction Cycle
Fctch and Decode
Determine the Type of Instruction
Regster-Reference Instruction
Memory-Reference Insttuctions
ANDtoAC
ADDtoAC
LDA: Load to AC
STA: Store AC
BUN: Branch Unconditiondly
BSA: Branch and Savt Retum Address
ISZ: Increment and Skip If Zero
Control Flowchart
Input-Output and Interrupt
Inpnt-Output Confiptrtion
Input-Output Instructions
Program lntevrvpt
Interrupt Cycle
Completc Computer Description
Design of Basic Computer
Control Logic Gotes
Control af Rcpsters and Memory
Control of Single Flip-Flops
Control af Common Bus
Design of Accumulator Logic
Control of AC Register
Adder and Lopc Circuit
Problems
Refcrences
CHAPTER SIX Programming the Basic Computer
Introduction
Machine Language
Assembly Language
Rules of the Longuage
An Exampte
Translation to Binary
The Assembler
Representation of Symbolic Program
in Memory
First Pass
Second Pass
Program Loops
Programming Arithmetic and Logic
Operations
MulriPlication Program
Doufcfe-Precision Addilion
Logic Operations
Shift Operations
Subroutines
Subroutmes Parameters md Data Lmtkage
Input-Output Programming
Character Manipulation
Program Interrvpt
Problems
References
CHAPTEK SEVEN Microprogrammed Control
Control Memory
Address Sequencing
Condiaonal Branchmg
Mappmg of Instrvction
Subroutmes
Microprogram Example
ComfPuter Configuration
Microinstrution Format
Symbolic: Microinstructions
The Fetch Routine
Sytnbolic Microprogram
Binary Microprogram
Design of Control Unit
Micioprogram Sequencer
Problems
References
CHAPTER EIGHT Central Processing Unit
8-1 Innoduction
8-2 General Register Organization
Control Word
Examples of Microoperations
8-3 Stack Organization
Register Stack
Memory Stack
Severse Polish Nottation
Evaluation af Arithmetic Expressions
8-4 Instmction Ponnats
Three-Address Instrctions
Two-Address Instructions
One-Address Instructions
Zero-Address Instructions
RISC Instrucrions
8-5 Addressing Modes
Numerical Example
8-6 Data Transfer and Manipulation
Data Transfer Instructions
Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
8-7 Program Control
Status Bit Conditions
Conditional Branch Instructions
Subroutine Call cmd Return
Program Interrupt
Types of Interrupts
8-8 Reduced Instruction Set Computer (RISC)
CISC Characteristics
RISC Choractenstics
Overlafiped Regisler Wmdows
Berkeley RISC 1
Problems
References
CHAPTER NINE Pipeline and Vector Processing
Parallel Processing
Pipelining
General Considerations
Arithmetic Pipeline
Instruction Pipeline
Example: Four-Segment Instruction Pipeline
Data Dependency
Handiing of Branch Inslructions
RISC Pipeline
Example: Three-Seemmt Instruction Pipeline
Delayed Load
Delayed Branch
Vector Processing
Vector Operations
Matrix Mulriplication
Memory Interleaving
Supercomputers
Array Processors
Atached Array Processor
SIMD Array Processor
Problems
Refcrences
CHAPTER TEN Computer Arithmetic
Introduction
Addition and Subtraction
Addition and Subtraction with Signed-Magnitude
Data
Hardware Implementation
Hardwore Algorithm
Addition and Subtraction with Signed
Complement Data
Multiplication Algorithms
Hardware Implementation for Signed-Magnitude
Ddta
Hardware Algorithm
Booih Multiplication Algorithm
Array Multjplier
Division Algorithms
Hardware Implementation for Signed-Magnitude
Data
Divide Overflow
Harduwe Algorithm
Other Algorithms
Floating-Point Arithmetic Operations
Basic Considerations
Repster Configruation
Addition and Subtracaon
Multiplication
Division
Decimal Arithmetic Unit
BCDAdder
BCD Subtraction
Decimal Arithmetic Operations
Addition and Subctroction
Muitiplicotion
Division
Floating-Point Operations
Problems
Rcferences
CHAPTER ELEVEN Input-Output Organization
Peripheral Devices
ASCII Alphanumeric Characters
Input-Output Interface
1/o Bus and Interface Modules
1/oversus Memory Bus
Isolaud versus Memory-Mapped 1/0
Exampfe af 1/o Interface
Asynchronous Daca Transfer
Strobe Control
Handshaking
Asynchronous Serial Transfer
Asynchronous Communication Interface
First-In, First-Out Buffer
Modes of Transfer
Exampk of Programmed 1/o
Interrupt-lnitiated 1/0
Softuare Consideration
Priority Interrupt
Daisy-Chainnig Priority
Parallel Priority Intersfpt
Pnority Encoder
Incerrupt Cycle
Software Routires
lnital and Firal Operations
Direct Memory Access (DMA)
DMAControlfer
DMA Tramfer
Input-Output Processor (IOP)
CPU-IOP Communication
IBM 370 1/0 Channel
Intel 8089 IOP
Serial Communication
Character-Oriented Protoco!
Transmission Example
Data Transparency
Bit-Orienetd Protocol
Problems
References
CHAPTER TWELVE Memory Organization
Mcmory Hierarchy
Main Memory
RAM and ROM Chips
Memory Address Map
Memory Connection to CPU
Auxiliary Memory
Magnetic Disks
Magnetic Tape
Associative Memory
Hardware Organization
Match Logic
Reod Operarion
Write Operation
Cache Memory
Associative Mapping
Dttect Mapping
Set-Associative Mapping
Writing mto Cache
Cache Initialization
Virtual Memory
Address Space and Memory Space
Address Mapping Using Pages
Associative Memory Page Table
Page Replacemtnt
Memory Management Hardware
Segmented-Page Mapping
Nuniercal Example
Memory Protection
Problems
References
CHAPTER THIRTEEN Multiprocessors
Characteristics of Multiprocessors
Interconnection Structures
Time-Shaxed Common Bus
Multiport Memory
Crossbar Switch
Multistage Switching Newwork
Hypercube IntCTConnecrion
Interprocessor Arbitration
System Bus
Serual Arbitration Procedure
Parallel ATbitration Logic
Dynamic Arbitrarion Algorithms
Inetprocessor Communication and
Synchronnation
Interprocessor Synchronization
Mutual Exclusion with a Semophore
Cache Coherence
Conditions for Incoherence
Soolutions to tht Cache Coherence Problem
Poblems
References
Index
CHAPTER ONE Digital Logic Circuits
1-1 Digital Computcrs
1-2 Logic Gates
Boolean Atgebra
1-3 Complement of a Fumction
Map Simplification
Product-of-Sums Simplification
1-4 Don't-Care Conditions
Combinational Circuits
1-5 Half-Adder
Full-Adder
1-6 Flip-Flops
SR Flip-Flop
DFlip-Flop
1-8 JK Flip-Flop
T Flip-Flop
Edge-TriggeredT Flip--Flops
Excitation Tables
Sequential Circuits
1-9 Flip-Flop input Equations
StateTable
State Diagram
Design Example
Design Procedure
Problems
CHAPTER TWO References
2-1 Integrated Cireuits
2-2 Decodeis
NAND Gate Decoder
Decoder Expansion
Encoders
2-3 Multiplewrs
2-4 Registcrs
register with Parallel Load
2-5 Shift Registers
Bidirectional Shift Register with Paraflel Load
2-6 Binary Counters
Binary Counter with Pa6rallel Load
2-7 Memory Unit
Random-Access Memory
Read-Only Memory
Types of ROMs
Problems
References
CHAPTER THREE Data Representation
DataTypcs
Number Systems
Octal and Hexadecimal Numbers
Dectmal Represention
Alphanumeric Representation
Complements
(r-l) Complement
(r's) Complement
Suberaction of Unsigned Numbers
Fixcd-Point Representation
Integer Represention
Arithonec Addition
Aruhmetic Subtraction
Ovverflow
Decimal Fixed-Pomt Representation
Floating-Point Representation
Other Binary Codes
GTay Code
Other Decimal Codes
Other Alphanumeric Codes
Error Detection Codes
Probkms
References
CHAPTER FOUR Register Transfer and Microoperations
Register Transfer Language
Register Transfer
Bus and Memory Transfers
Three-State Bus Buffers
Memory Transfer
Arithmetic Micrboperations
Binary Adder
Binary Adder-Subtactor
Binary Jncrementer
Arithmetic Circuit
Logic Microoperations
List of Logic Microoperations
Hardware ImpJementotion
Some Applications
Shift Microoperations
Hardware Implementation
Arithmetic Logic Shift Unit
Problems
References
CHAPTEK FIVE Basic Computer Organization and Design
Instruction Codes
Stored Program Organitaoon
indirect Address
Computer Registers
Common Bus System
Computer Instructions
Imtrucrion Set Completeness
Tuning and Control
Inscruction Cycle
Fctch and Decode
Determine the Type of Instruction
Regster-Reference Instruction
Memory-Reference Insttuctions
ANDtoAC
ADDtoAC
LDA: Load to AC
STA: Store AC
BUN: Branch Unconditiondly
BSA: Branch and Savt Retum Address
ISZ: Increment and Skip If Zero
Control Flowchart
Input-Output and Interrupt
Inpnt-Output Confiptrtion
Input-Output Instructions
Program lntevrvpt
Interrupt Cycle
Completc Computer Description
Design of Basic Computer
Control Logic Gotes
Control af Rcpsters and Memory
Control of Single Flip-Flops
Control af Common Bus
Design of Accumulator Logic
Control of AC Register
Adder and Lopc Circuit
Problems
Refcrences
CHAPTER SIX Programming the Basic Computer
Introduction
Machine Language
Assembly Language
Rules of the Longuage
An Exampte
Translation to Binary
The Assembler
Representation of Symbolic Program
in Memory
First Pass
Second Pass
Program Loops
Programming Arithmetic and Logic
Operations
MulriPlication Program
Doufcfe-Precision Addilion
Logic Operations
Shift Operations
Subroutines
Subroutmes Parameters md Data Lmtkage
Input-Output Programming
Character Manipulation
Program Interrvpt
Problems
References
CHAPTEK SEVEN Microprogrammed Control
Control Memory
Address Sequencing
Condiaonal Branchmg
Mappmg of Instrvction
Subroutmes
Microprogram Example
ComfPuter Configuration
Microinstrution Format
Symbolic: Microinstructions
The Fetch Routine
Sytnbolic Microprogram
Binary Microprogram
Design of Control Unit
Micioprogram Sequencer
Problems
References
CHAPTER EIGHT Central Processing Unit
8-1 Innoduction
8-2 General Register Organization
Control Word
Examples of Microoperations
8-3 Stack Organization
Register Stack
Memory Stack
Severse Polish Nottation
Evaluation af Arithmetic Expressions
8-4 Instmction Ponnats
Three-Address Instrctions
Two-Address Instructions
One-Address Instructions
Zero-Address Instructions
RISC Instrucrions
8-5 Addressing Modes
Numerical Example
8-6 Data Transfer and Manipulation
Data Transfer Instructions
Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
8-7 Program Control
Status Bit Conditions
Conditional Branch Instructions
Subroutine Call cmd Return
Program Interrupt
Types of Interrupts
8-8 Reduced Instruction Set Computer (RISC)
CISC Characteristics
RISC Choractenstics
Overlafiped Regisler Wmdows
Berkeley RISC 1
Problems
References
CHAPTER NINE Pipeline and Vector Processing
Parallel Processing
Pipelining
General Considerations
Arithmetic Pipeline
Instruction Pipeline
Example: Four-Segment Instruction Pipeline
Data Dependency
Handiing of Branch Inslructions
RISC Pipeline
Example: Three-Seemmt Instruction Pipeline
Delayed Load
Delayed Branch
Vector Processing
Vector Operations
Matrix Mulriplication
Memory Interleaving
Supercomputers
Array Processors
Atached Array Processor
SIMD Array Processor
Problems
Refcrences
CHAPTER TEN Computer Arithmetic
Introduction
Addition and Subtraction
Addition and Subtraction with Signed-Magnitude
Data
Hardware Implementation
Hardwore Algorithm
Addition and Subtraction with Signed
Complement Data
Multiplication Algorithms
Hardware Implementation for Signed-Magnitude
Ddta
Hardware Algorithm
Booih Multiplication Algorithm
Array Multjplier
Division Algorithms
Hardware Implementation for Signed-Magnitude
Data
Divide Overflow
Harduwe Algorithm
Other Algorithms
Floating-Point Arithmetic Operations
Basic Considerations
Repster Configruation
Addition and Subtracaon
Multiplication
Division
Decimal Arithmetic Unit
BCDAdder
BCD Subtraction
Decimal Arithmetic Operations
Addition and Subctroction
Muitiplicotion
Division
Floating-Point Operations
Problems
Rcferences
CHAPTER ELEVEN Input-Output Organization
Peripheral Devices
ASCII Alphanumeric Characters
Input-Output Interface
1/o Bus and Interface Modules
1/oversus Memory Bus
Isolaud versus Memory-Mapped 1/0
Exampfe af 1/o Interface
Asynchronous Daca Transfer
Strobe Control
Handshaking
Asynchronous Serial Transfer
Asynchronous Communication Interface
First-In, First-Out Buffer
Modes of Transfer
Exampk of Programmed 1/o
Interrupt-lnitiated 1/0
Softuare Consideration
Priority Interrupt
Daisy-Chainnig Priority
Parallel Priority Intersfpt
Pnority Encoder
Incerrupt Cycle
Software Routires
lnital and Firal Operations
Direct Memory Access (DMA)
DMAControlfer
DMA Tramfer
Input-Output Processor (IOP)
CPU-IOP Communication
IBM 370 1/0 Channel
Intel 8089 IOP
Serial Communication
Character-Oriented Protoco!
Transmission Example
Data Transparency
Bit-Orienetd Protocol
Problems
References
CHAPTER TWELVE Memory Organization
Mcmory Hierarchy
Main Memory
RAM and ROM Chips
Memory Address Map
Memory Connection to CPU
Auxiliary Memory
Magnetic Disks
Magnetic Tape
Associative Memory
Hardware Organization
Match Logic
Reod Operarion
Write Operation
Cache Memory
Associative Mapping
Dttect Mapping
Set-Associative Mapping
Writing mto Cache
Cache Initialization
Virtual Memory
Address Space and Memory Space
Address Mapping Using Pages
Associative Memory Page Table
Page Replacemtnt
Memory Management Hardware
Segmented-Page Mapping
Nuniercal Example
Memory Protection
Problems
References
CHAPTER THIRTEEN Multiprocessors
Characteristics of Multiprocessors
Interconnection Structures
Time-Shaxed Common Bus
Multiport Memory
Crossbar Switch
Multistage Switching Newwork
Hypercube IntCTConnecrion
Interprocessor Arbitration
System Bus
Serual Arbitration Procedure
Parallel ATbitration Logic
Dynamic Arbitrarion Algorithms
Inetprocessor Communication and
Synchronnation
Interprocessor Synchronization
Mutual Exclusion with a Semophore
Cache Coherence
Conditions for Incoherence
Soolutions to tht Cache Coherence Problem
Poblems
References
Index
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