书籍详情
VHDL设计、表示和综合：英文版
作者：（美）James R.Armstrong，（美）F.Gail Gray著
出版社：机械工业出版社
出版时间：2003-03-01
ISBN：9787111116769
定价：¥69.00
购买这本书可以去
内容简介
VHDL语言是一种主流的硬件描述语言。本书既不同于一般的VHDL语言教材，也区别于传统的关于逻辑设计的书籍，它把VHDL语言的介绍融合到了不同抽象层次的设计中，全面深入地讲述了从原始的高层模型到门级实现的各层次的设计技术，并辅以典型实例，既能使读者对有关数字系统设计的知识有一个全面了解，同时又能较好地掌握VHDL语言及其在不同设计层次中的应用方法，掌握基于VHDL的设计技术。本书比较注重设计方法和基本概念的介绍，深入浅出，每章还配备了大量针对性很强的习题，非常适合作为电子工程、计算机等专业VLSI设计相关课程的本科生和研究生教材，也可供相关的工程技术人员参考。对于打算自学这方面内容的人来说，本书也是一本不可多得的好书。
作者简介
JamesR.Armstrong博士是弗吉尼亚理工大学（VirginiaTech）电机与计算机工程系的教授，VHDL方面的国际权威。IEEE标准化委员会的创始成员以及IEEEVHDL标准化工作级和设计自动化荼组的主席。F.GailGray博士是弗吉尼亚理工大学（VirginiaTech）电机与计算机工程系的教授。拥有密歇根大学计算机、信息和控制工程博士学位。
目录
1 Structured Design Concepts
1.1 The Abstraction Hierarchy
1.2 Textual vs.Pictorial Representations
1.3 Types of Behavioral Descriptions
1.4 Design Process
1.5 Structural Design Decomposition
1.6 The DigitalDesign Space
2 Design Tools
2.1 CAD Tool Taxonomy
2.1.1 Editors
2.1.2 Simulators
2.1.3 Checkers and Analyzers
2.1.4 Optimizers and Synthesizers
2.1.5 Cad Systems
2.2 Schematic Editors
2.3 Simulators
2.3.1 Simulation Cycle
2.3.2 Simulator Organization
2.3.3 Language Scheduling Mechanism
2.3.4 Simulation Effciency
2.4 The Simulation System
2.5 Simulation Aids
2.5.1 Model Preparation
2.5.2 Model Test Vector Development
2.5.3 Model Debugging
2.5.4 Results Interpretation
2.6 Applications of Simulation
2.7 Synthesis Tools
3 Basic Features of VHDL
3.1 Major Language Constructs
3.1.1 Design Entities
3.1.2 Architectural Bodies
3.1.3 Model Testing
3.1.4 Block Statements
3.1.5 Processes
3.1.6
3.2 Lexical Description
3.2.1 Character Set
3.2.2 Lexical Elements
3.2.3 Delimiters
3.2.4 Identifiers
3.2.5 Comments
3.2.6 Character Literal
3.2.7 String Literal
3.2.8 Bit String Literal
3.2.9 Abstract Literal
3.2.10 Decimal Literal
3.2.11 Based Literal
3.3 VHDL Source File
3.4 Data Types
3.4.1 Classification of Types
3.4.2 Scalar Data Types
3.4.3 Composite Data Types
3.4.4 Access Types
3.4.5 File Types
3.4.6 Type Marks
3.5 Data Objects
3.5.1 Classes of Objects
3.5.2 Declaration of Data Objects
3.6 Language Statements
3.6.1 Assignment Statements
3.6.2 Operators and Expressions
3.6.3 Sequential Control Statements
3.6.4 Architecture Declarations and Concurrent Statements
3.6.5 Subprograms
3.7 Advanced Features of VHDL
3.7.1 Overloading
3.7.2 Packages
3.7.3 Visibility
3.7.4 Libraries
3.7.5 Configurations
3.7.6 File I/O
3.8 The Formal Nature of VHDL
3.9 VHDL
3.9.1 Lexical Character Set
3.9.2 Syntax Changes
3.9.3 Proces and Signal Timing and New Signal Attributes
3.9.4 New Operators
3.9.5 Improvements to Structural Models
3.9.6 Shared Variables
3.9.7 Improved Reporting Capability
3.9.8 General programming Features
3.9.9 File I/O
3.9.10 Groups
3.9.11 Extension of Bit String Literals
3.9.12 Additions and Changes to Package Standard
3.10 Summary
4 Basic VHDL Modeling Techniques
4.1 Modeling Delay in VHDL
4.1.1 Propagation Delay
4.1.2 Delay and Concurrency
4.1.3 Sequential and Concurrent Statements in VHDL
4.1.4 Implementation of Time Delay in the VHDL Simulator
4.1.5 Inertial and Transport Delay in Signal Propagation
4.2 The VHDL Scheduling Algorithm
4.2.1 Waveform Updating
4.2.2 Side Effects
4.3 Modeling Combinational and Sequential Logic
4.4 Logic Primitives
4.4.1 Combinational Logic Primitives
4.4.2 SEQUENTIAL LOGIC
4.4.3 Testing Models:Test Bench Development
5 Algorithmic Level Design
5.1 General Algorithmic Model Development in the Behavioral Domain
5.1.1 Process Model Graph
5.1.2 Algorithmic Model of a Parallel to Serial Converter
5.1.3 Algorithmic Models with Timing
5.1.4 Checking Timing
5.2 Representation of System Interconnections
5.2.1 Comprehensive Algorithmic Modeling Example
5.3 Algorithmic Modeling of Systems
5.3.1 Multivalued Logic Systems
5.3.2 Comprehensive System Example
5.3.3 Time Multiplexing
6 Register Level Design
6.1 Transition from Algorithmic to Data Flow Descriptions
6.1.1 Transformation Example
6.2 Timing Analysis
6.3 Control Unit Design
6.3.1 Types of Control Units
6.4 Ultimate RISC Machine
6.4.1 Single URISC Machine
6.4.2 URISC Architecture
6.4.3 URISC Control
6.4.4 URISC System
6.4.5 Design of the URISC at the Register Level
6.4.6 Microcoded Controller for the URISC Processor
6.4.7 Hardwired Controlller for the URISC Processor
7 Gate Leveland ASIC Library Modeling
7.1 Accurate Gate Level Modeling
7.1.1 Asymmetric Timing
7.1.2 Load Sensitive Delay Modeling
7.1.3 ASIC Cell Delay Modeling
7.1.4 Back Annotation of Delays
7.1.5 VITAL:A Standard for the Generation of VHDL Models of Library Elements
7.2 Error Checking
7.3 Multivalued Logic for Gate Level Modeling
7.3.1 Additional Values for MOS Design
7.3.2 Generalized State/Strength Model
7.3.3 Interval Logic
7.3.4 Vantage System
7.3.5 Multivalued Gate-Level Models
7.3.6 Accurate Delay Modeling
7.4 Configuration DEclarations for Gate Level Models
7.4.1 Default Configuration
7.4.2 Configurations and Component Libraries
7.5 Modeling Races and Hazards
7.6 Approaches to Delay Control
8 HDL-Based Design Techniques
8.1 Design of Combinational Logic Circuits
8.1.1 Conbinational Logic Design at the Algorithmic Level
8.1.2 Design of Data Flow Models of Combinational Logic in the Behavioral Domain
8.1.3 Synthesis of Gate-Level Structural Domain Combinational Logic Circuits
8.1.4 Summary of Design Activity for Combinational Logic Circuits
8.2 Design of Sequential Logic Circuits
8.2.1 Moore or Mealy Decision
8.2.2 Construction of a State Table
8.2.3 Creating a State Diagram
8.2.4 Transition List Approach
8.2.5 Creating a VHDL Model for State Machines
8.2.6 Synthesis of VHDL State Machine Models
8.3 Design of Microprogrammed Control Units
8.3.1 Interface Between Controller and Device
8.3.2 Comparison of Hardwired and Microprogrammed Control Units
8.3.3 Basic Microprogrammed Control Unit
8.3.4 Algorithmic-Level Model of BMCU
8.3.5 Design of Microprogrammed Controllers for State Machines
8.3.6 Generalities and Limitations of Microprogrammed Control Units
8.3.7 Alternative Condition Select Methods
8.3.8 Alternative Branching Methods
9 ASICs and the ASIC Design Process
9.1 What is and ASIC?
9.2 ASIC Circuit Technology
9.2.1 CMOS Switches
9.3 Types of ASICs
9.3.1 PLDs
9.3.2 Field Programmable Gate Arrays
9.3.3 Gate Arrays
9.3.4 Standard Cells
9.3.5 Full Custom Chips
9.3.6 Relative Cost of ASICs and FPGAs
9.4 The ASIC Design Process
9.4.1 Standard Cell ASIC Synthesis
9.4.2 Post Synthesis Simulation
9.5 FPGA Synthesis
9.5.1 FPGA Example
9.5.2 Comparison with and ASIC Design
10 Modeling for Synthesis
10.1 Behavioral Model Development
10.1.1 Creation of the Initial Behavioral Model
10.1.2 Application-Domain Tools
10.1.3 Language-Domain Modeling
10.1.4 Modeling and Model Efficiency
10.1.5 Application-Domain vs.Language-Domain Modeling
10.2 The Semantics of Simulation and Synthesis
10.2.1 Delay in Models
10.2.2 Data Types
10.3 Modeling Sequential Behavior
10.4 Modeling Combinational Circuits for Synthesis
10.4.1 Synthesis of Arithmetic Circuits
10.4.2 Hierarchical Arithmetic Circuit:BCD to Binary Converter
10.4.3 Synthesis of Hierarchical Circuits
10.5 Inferred Lathces and Don't Cares
10.6 Tristate Circuits
10.7 Shared Resources
10.8 Flattening and Structuring
10.9 Effect of Modeling Style On Circult Complexity
10.9.1 Effect of Selection of Individual Construct
10.9.2 Effect of General Modeling Approach
11 Integration of VHDL into a Top-Down Design Methodology
11.1 Top-Down Design Methodology
11.2 Sobel Edge Detection Algorithm
11.3 System Requirements Level
11.3.1 Written Specifications
11.3.2 Requirements Repository
11.4 System Definition Level
11.4.1 Executable Specification
11.4.2 Test Bench Development for Executable Specifications
11.5 Architecture Design
11.5.1 System Level Decomposition
11.5.2 Hierarchical Decomposition
11.5.3 Methodology for Development of Test Benches for a Hierarchical Structural Model
11.6 Detailed Design at the RTL Level
11.6.1 Register Transfer Level Design
11.6.2 Simulating Structural Models Using Components with Different Data Types
11.6.3 Test Bench Development at the RTL
11.7 Detailed Design at the Gate Level
11.7.1 Gate-Level Design of Horizontal Filter
11.7.2 Optimization of Gate-Level Circuits
11.7.3 Gate-Level Testing
11.7.4 Methodology for Back Annotation
12 Synthesis Algorithms for Design Automation
12.1 Benefits of Algorithmic Synthesis
12.2 Algorithmic Synthesis Tasks
12.2.1 Compilation of VHDL Description into an Interanl Format
12.2.2 Scheduling
12.2.3 Allocation
12.2.4 Interaction of Scheduling and Allocation
12.2.5 Gantt Charts and Utilization
12.2.6 Creating FSM VHDL from an Allocation Graph
12.3 Scheduling Techniques
12.3.1 Transformational Scheduling
12.3.2 Iterative/Constructive Scheduling
12.3.3 ASAP Scheduling
12.3.4 ALAP Scheduling
12.3.5 List Scheduling
12.3.6 Freedom-Directed Scheduling
12.4 Allocation Techniques
12.4.1 Greedy Aoolcation
12.4.2 Allocation by Exhaustive Search
12.4.3 Left Edge Algorithm
12.4.4 Assigning Functional Units and Interconnection Paths
12.4.5 Analysis of the Allocation Process
12.4.6 Nearly Minimal Cluster Partitioning Algorithm
12.4.7 Profit Directed Cluster Partitioning Algorithm(PDCPA)
12.5 State of the Art in High-Level Synthesis
12.6 Automated Synthesis of VHDL Constructs
12.6.1 Constructs that Involve Selection
12.6.2 Mapping case Statements to Multiplexers
12.6.3 Mapping if...then...else Statements to Multiplexers
12.6.4 Mapping Indexed Vector References to Multiplexers
12.6.5 Loop Constructs
12.6.6 Functions and Procedures
1.1 The Abstraction Hierarchy
1.2 Textual vs.Pictorial Representations
1.3 Types of Behavioral Descriptions
1.4 Design Process
1.5 Structural Design Decomposition
1.6 The DigitalDesign Space
2 Design Tools
2.1 CAD Tool Taxonomy
2.1.1 Editors
2.1.2 Simulators
2.1.3 Checkers and Analyzers
2.1.4 Optimizers and Synthesizers
2.1.5 Cad Systems
2.2 Schematic Editors
2.3 Simulators
2.3.1 Simulation Cycle
2.3.2 Simulator Organization
2.3.3 Language Scheduling Mechanism
2.3.4 Simulation Effciency
2.4 The Simulation System
2.5 Simulation Aids
2.5.1 Model Preparation
2.5.2 Model Test Vector Development
2.5.3 Model Debugging
2.5.4 Results Interpretation
2.6 Applications of Simulation
2.7 Synthesis Tools
3 Basic Features of VHDL
3.1 Major Language Constructs
3.1.1 Design Entities
3.1.2 Architectural Bodies
3.1.3 Model Testing
3.1.4 Block Statements
3.1.5 Processes
3.1.6
3.2 Lexical Description
3.2.1 Character Set
3.2.2 Lexical Elements
3.2.3 Delimiters
3.2.4 Identifiers
3.2.5 Comments
3.2.6 Character Literal
3.2.7 String Literal
3.2.8 Bit String Literal
3.2.9 Abstract Literal
3.2.10 Decimal Literal
3.2.11 Based Literal
3.3 VHDL Source File
3.4 Data Types
3.4.1 Classification of Types
3.4.2 Scalar Data Types
3.4.3 Composite Data Types
3.4.4 Access Types
3.4.5 File Types
3.4.6 Type Marks
3.5 Data Objects
3.5.1 Classes of Objects
3.5.2 Declaration of Data Objects
3.6 Language Statements
3.6.1 Assignment Statements
3.6.2 Operators and Expressions
3.6.3 Sequential Control Statements
3.6.4 Architecture Declarations and Concurrent Statements
3.6.5 Subprograms
3.7 Advanced Features of VHDL
3.7.1 Overloading
3.7.2 Packages
3.7.3 Visibility
3.7.4 Libraries
3.7.5 Configurations
3.7.6 File I/O
3.8 The Formal Nature of VHDL
3.9 VHDL
3.9.1 Lexical Character Set
3.9.2 Syntax Changes
3.9.3 Proces and Signal Timing and New Signal Attributes
3.9.4 New Operators
3.9.5 Improvements to Structural Models
3.9.6 Shared Variables
3.9.7 Improved Reporting Capability
3.9.8 General programming Features
3.9.9 File I/O
3.9.10 Groups
3.9.11 Extension of Bit String Literals
3.9.12 Additions and Changes to Package Standard
3.10 Summary
4 Basic VHDL Modeling Techniques
4.1 Modeling Delay in VHDL
4.1.1 Propagation Delay
4.1.2 Delay and Concurrency
4.1.3 Sequential and Concurrent Statements in VHDL
4.1.4 Implementation of Time Delay in the VHDL Simulator
4.1.5 Inertial and Transport Delay in Signal Propagation
4.2 The VHDL Scheduling Algorithm
4.2.1 Waveform Updating
4.2.2 Side Effects
4.3 Modeling Combinational and Sequential Logic
4.4 Logic Primitives
4.4.1 Combinational Logic Primitives
4.4.2 SEQUENTIAL LOGIC
4.4.3 Testing Models:Test Bench Development
5 Algorithmic Level Design
5.1 General Algorithmic Model Development in the Behavioral Domain
5.1.1 Process Model Graph
5.1.2 Algorithmic Model of a Parallel to Serial Converter
5.1.3 Algorithmic Models with Timing
5.1.4 Checking Timing
5.2 Representation of System Interconnections
5.2.1 Comprehensive Algorithmic Modeling Example
5.3 Algorithmic Modeling of Systems
5.3.1 Multivalued Logic Systems
5.3.2 Comprehensive System Example
5.3.3 Time Multiplexing
6 Register Level Design
6.1 Transition from Algorithmic to Data Flow Descriptions
6.1.1 Transformation Example
6.2 Timing Analysis
6.3 Control Unit Design
6.3.1 Types of Control Units
6.4 Ultimate RISC Machine
6.4.1 Single URISC Machine
6.4.2 URISC Architecture
6.4.3 URISC Control
6.4.4 URISC System
6.4.5 Design of the URISC at the Register Level
6.4.6 Microcoded Controller for the URISC Processor
6.4.7 Hardwired Controlller for the URISC Processor
7 Gate Leveland ASIC Library Modeling
7.1 Accurate Gate Level Modeling
7.1.1 Asymmetric Timing
7.1.2 Load Sensitive Delay Modeling
7.1.3 ASIC Cell Delay Modeling
7.1.4 Back Annotation of Delays
7.1.5 VITAL:A Standard for the Generation of VHDL Models of Library Elements
7.2 Error Checking
7.3 Multivalued Logic for Gate Level Modeling
7.3.1 Additional Values for MOS Design
7.3.2 Generalized State/Strength Model
7.3.3 Interval Logic
7.3.4 Vantage System
7.3.5 Multivalued Gate-Level Models
7.3.6 Accurate Delay Modeling
7.4 Configuration DEclarations for Gate Level Models
7.4.1 Default Configuration
7.4.2 Configurations and Component Libraries
7.5 Modeling Races and Hazards
7.6 Approaches to Delay Control
8 HDL-Based Design Techniques
8.1 Design of Combinational Logic Circuits
8.1.1 Conbinational Logic Design at the Algorithmic Level
8.1.2 Design of Data Flow Models of Combinational Logic in the Behavioral Domain
8.1.3 Synthesis of Gate-Level Structural Domain Combinational Logic Circuits
8.1.4 Summary of Design Activity for Combinational Logic Circuits
8.2 Design of Sequential Logic Circuits
8.2.1 Moore or Mealy Decision
8.2.2 Construction of a State Table
8.2.3 Creating a State Diagram
8.2.4 Transition List Approach
8.2.5 Creating a VHDL Model for State Machines
8.2.6 Synthesis of VHDL State Machine Models
8.3 Design of Microprogrammed Control Units
8.3.1 Interface Between Controller and Device
8.3.2 Comparison of Hardwired and Microprogrammed Control Units
8.3.3 Basic Microprogrammed Control Unit
8.3.4 Algorithmic-Level Model of BMCU
8.3.5 Design of Microprogrammed Controllers for State Machines
8.3.6 Generalities and Limitations of Microprogrammed Control Units
8.3.7 Alternative Condition Select Methods
8.3.8 Alternative Branching Methods
9 ASICs and the ASIC Design Process
9.1 What is and ASIC?
9.2 ASIC Circuit Technology
9.2.1 CMOS Switches
9.3 Types of ASICs
9.3.1 PLDs
9.3.2 Field Programmable Gate Arrays
9.3.3 Gate Arrays
9.3.4 Standard Cells
9.3.5 Full Custom Chips
9.3.6 Relative Cost of ASICs and FPGAs
9.4 The ASIC Design Process
9.4.1 Standard Cell ASIC Synthesis
9.4.2 Post Synthesis Simulation
9.5 FPGA Synthesis
9.5.1 FPGA Example
9.5.2 Comparison with and ASIC Design
10 Modeling for Synthesis
10.1 Behavioral Model Development
10.1.1 Creation of the Initial Behavioral Model
10.1.2 Application-Domain Tools
10.1.3 Language-Domain Modeling
10.1.4 Modeling and Model Efficiency
10.1.5 Application-Domain vs.Language-Domain Modeling
10.2 The Semantics of Simulation and Synthesis
10.2.1 Delay in Models
10.2.2 Data Types
10.3 Modeling Sequential Behavior
10.4 Modeling Combinational Circuits for Synthesis
10.4.1 Synthesis of Arithmetic Circuits
10.4.2 Hierarchical Arithmetic Circuit:BCD to Binary Converter
10.4.3 Synthesis of Hierarchical Circuits
10.5 Inferred Lathces and Don't Cares
10.6 Tristate Circuits
10.7 Shared Resources
10.8 Flattening and Structuring
10.9 Effect of Modeling Style On Circult Complexity
10.9.1 Effect of Selection of Individual Construct
10.9.2 Effect of General Modeling Approach
11 Integration of VHDL into a Top-Down Design Methodology
11.1 Top-Down Design Methodology
11.2 Sobel Edge Detection Algorithm
11.3 System Requirements Level
11.3.1 Written Specifications
11.3.2 Requirements Repository
11.4 System Definition Level
11.4.1 Executable Specification
11.4.2 Test Bench Development for Executable Specifications
11.5 Architecture Design
11.5.1 System Level Decomposition
11.5.2 Hierarchical Decomposition
11.5.3 Methodology for Development of Test Benches for a Hierarchical Structural Model
11.6 Detailed Design at the RTL Level
11.6.1 Register Transfer Level Design
11.6.2 Simulating Structural Models Using Components with Different Data Types
11.6.3 Test Bench Development at the RTL
11.7 Detailed Design at the Gate Level
11.7.1 Gate-Level Design of Horizontal Filter
11.7.2 Optimization of Gate-Level Circuits
11.7.3 Gate-Level Testing
11.7.4 Methodology for Back Annotation
12 Synthesis Algorithms for Design Automation
12.1 Benefits of Algorithmic Synthesis
12.2 Algorithmic Synthesis Tasks
12.2.1 Compilation of VHDL Description into an Interanl Format
12.2.2 Scheduling
12.2.3 Allocation
12.2.4 Interaction of Scheduling and Allocation
12.2.5 Gantt Charts and Utilization
12.2.6 Creating FSM VHDL from an Allocation Graph
12.3 Scheduling Techniques
12.3.1 Transformational Scheduling
12.3.2 Iterative/Constructive Scheduling
12.3.3 ASAP Scheduling
12.3.4 ALAP Scheduling
12.3.5 List Scheduling
12.3.6 Freedom-Directed Scheduling
12.4 Allocation Techniques
12.4.1 Greedy Aoolcation
12.4.2 Allocation by Exhaustive Search
12.4.3 Left Edge Algorithm
12.4.4 Assigning Functional Units and Interconnection Paths
12.4.5 Analysis of the Allocation Process
12.4.6 Nearly Minimal Cluster Partitioning Algorithm
12.4.7 Profit Directed Cluster Partitioning Algorithm(PDCPA)
12.5 State of the Art in High-Level Synthesis
12.6 Automated Synthesis of VHDL Constructs
12.6.1 Constructs that Involve Selection
12.6.2 Mapping case Statements to Multiplexers
12.6.3 Mapping if...then...else Statements to Multiplexers
12.6.4 Mapping Indexed Vector References to Multiplexers
12.6.5 Loop Constructs
12.6.6 Functions and Procedures
猜您喜欢
