书籍详情
数字逻辑与计算机硬件设计基础（英文原版）
作者：（美）M.Morris Mano著，（美）Charles R.Kime著
出版社：电子工业出版社
出版时间：2002-07-01
ISBN：9787505376625
定价：¥58.00
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内容简介
本书是计算机科学、计算机工程和电气工程等专业的学生学习逻辑电路设计的入门教程。全书共7章和一个附录，前4章介绍数制、开关代数、真值表和卡诺图，并讲解了逻辑函数的化简以及组合系统的分析与设计；后3章介绍时序系统的分析与设计、移位寄存器和计数器、可编程逻辑器件、用列表法和状态分割法进行状态化简和状态分配；附录部分介绍了4个实验操作平台及25个实验室作业。要学好逻辑电路设计这门课程，需要掌握好三个环节：理论、习题和实验。本书紧紧抓住这些教学环节，系统地阐述了逻辑设计的核心内容，尤其突出了系统的分析和设计方法。对于需要学生通过练习进一步巩固的重点内容，书中均布置了适量作业。在每章讲述内容之后专门安排了一节解题实例和一节习题。本书是学习逻辑电路设计难得的一本好教材，既可作为计算机、电气工程和通信、电子等专业学生的教材或教学参考书，也可供相关专业工程技术人员参考。译者序《逻辑电路设计基础》是计算机、电气工程及通信、电子等专业学生的一门重要的技术基础课。因此，学好本门课程，是对以上各个专业学生的一个基本要求。为了帮助中国学生学好这门课程，电子工业出版社引进了《逻辑电路设计基础》一书。该书紧紧抓住理论、习题和实践等教学环节，理论与实践并重，是一本很有特色的教材。本书全面系统地阐述了逻辑电路设计的核心内容，尤其突出了系统的分析和设计方法。本书的特点体现在如下几个方面：1．内容深入浅出问题的讲授总是先从给读者一个粗略的总体概念开始，譬如第1章即给出了组合逻辑设计的过程，使读者对逻辑设计有一个初步了解，不致使学生在后面内容的学习中对问题感到茫然，然后介绍逻辑设计过程中各个步骤所需的理论、工具和方法，再到整个系统的设计。做到由浅入深，从个别到一般，把内容逐步扩展开来，直到把问题讲述得十分透彻。2．实用性强这主要体现在三个方面，一是书中有大量的例题、解题实例和习题，使学生便于学习和掌握书中介绍的各种方法和技巧，也便于自学；二是分析和设计所用的电路大多是商用的集成电路芯片，使学生在学习过程中即完成了从原理电路到真实电路的过渡，提高实际应用能力；三是在附录中介绍了四种实验平台，提供许多实验室作业，使学生能理论联系实际，进一步巩固所学知识。3．优化设计优化设计既可降低实现成本，又能减小电路的体积和提高电路的可靠性。这是本书始终贯穿的基本思想，从逻辑函数的化简求最优解，到组合逻辑电路设计时所用的门数最少、芯片数最少、芯片的种类最少、芯片之间的连线最少，再到时序电路设计时通过状态化简和状态分配，使所用存储电路最少、组合逻辑最少等。在求最优解的过程中，提炼出一些规范性的化简方法，如迭代合意法化简逻辑函数、状态分割法进行状态化简和状态分配等，都体现了这一思想。使学生？谘罢庋幻抛ㄒ祷】蔚氖焙颍跃醯匮梢？个“经济头脑”，从而在实际设计中，力争最优。4．适于作为大学生的教材本书是作者多年教学工作的总结，其手稿征求过美国许多大学同行们的意见，并且，前期书稿由作者本人及其同事进行过多个轮次的教学。最后经过多所大学的同行审阅，几经修改才正式出版。在书的前言部分作者给出了各部分内容的参考学时数，并根据不同具体情况对内容的取舍，供老师们在教学中参考，因此，本书非常适于作为大学生的教材或教学参考书。本书的前言及第1章由杨匡汉教授翻译；第2～6章由殷洪玺博士翻译；第7章和附录由李正斌博士翻译。由殷洪玺博士对全书译稿作了统一校订，最后由徐安士教授审阅了全书。书中出现的名词术语，本着“名从主人”的原则，一般都选用国内较为通用的译名。对于一些还没有通用译名的术语，译者本着“一名之立，旬月踌躇”的精神，反复推敲，才把译名定下来。例如第3章提到的“迭代合意法”（IteratedConsensus）和第5章谈到的“时序径迹”（TimingTrace）等。由于译者水平有限，加之时间匆促，译文中的不妥之处，希望广大读者给予批评指正。
作者简介
暂缺《数字逻辑与计算机硬件设计基础（英文原版）》作者简介
目录
Chapter 1 3
DIGlTAL COMPUTERS AND INFORMATION
1-1 Digital Computers
Information Representation
Computer Structure
More on the Generic Computer
1-2 Number Systems
Binary Numbers
Octal and Hexadecimal Numbers
Number Ranges
1-3 Arithmetic Operations
Conversion from Decimal to Other Bases
1-4 Decimal Codes
BCD Addition
1-5 Alphanumeric Codes
ASCII Character Code
Parity Bit
1-6 Chapter Sununary
References
Problems
CHAPTER 2 27
COMBINATIONAL LOGIC CIRCUITS
2-1 Binary Logic and Gates
Binary Logic
Logic Gates
2-2 Boolean Algebra
Basic Identities of Boolean Algebra
Algebraic Manipulation
Complement of a Function
2-3 Standard Forms
Minterms and Maxterms
Sum of Products
Product of Sums
2-4 Map Simplification
Two-Variable Map
Me-Variable Map
Four-Variable Map
2-5 Map Manipulation
Essential Prime Implicants
Nonessential Prime Implicants
Product-of Sums Simplification
Don't--Care Condihons
2-6 NAND and NOR Gates
NAND Circuits
Two-Level Implementation
Multi1evel NAND Circuits
NOR Circuits
2-7 Exclusive-OR Gates
Odd Function
Parity Generation and Checking
2-8 Integrated Circuits
Levels of Integration
Digital Logic Families
Positive and Negative Logic
Transmission Gates
2-9 Chapter Sununary
References
Problems
CHAPTER 3
COMBINATIONAL LOGIC DESIGN
3-1 Combinational Circuits
3-2 Design Topics
Design Hierarchy
Top-Down Design
Computer-Aided Design
Hardware Description Languages
Logic Synthesis
3-3 Analysis Procedure
Derivation of Boolean Functions
Derivation of the Truth Table
Logic Simulation
3-4 Design Procedure
Code Converters
3-5 Decoders
Decoder Expansion
Combinahonal Circuit Implemenation
3-6 Enceders
Priority Encoder
3-7 Multiplexers
Combinahonal Circuit Implementation
Demultiplexer
3-8 Binare Adders
Half Adder
Full Adder
Binare Ripple Carry Adder
Cap Lookahead Aduer
3-9 Binary Subtraction
Complements
Subtraction with Complements
3-10 Binary Adder-Subtractors
Signed Binary Numbers
Signed Binary Addition and Subtraction
Overflow
3-11 Binny Multipliers
3-12 Decimal Arithmetic
Use of Complements in Decimal
3-13 HDL Representations -- VHDL
Structural Description
Dataflow Description
Hierarchical Description
Behavioral Description
3-14 HDL Representations - Verilog
Structural Description
Dataflow Description
Hierarchical Description
Behavioral Description
3-15 Chapter Sununary
References
Problems
CHAPTER 4 183
SEQUENTIAL CIRCUITS
4-1 Sequential Circuit Definitions
4-2 Latches
SR and S R Latches
D Latch
4-3 Flip-Flops
Master-Slave Flip-Flop
Edge-Triggered Flip-Flop
Standard Graphics Symbols
Characteristic Tables
Direct Inputs
4-4 Sequential Circuit Analysis
Input Equations
State Table
Analysis with JK Flip-Flops
State Diagram
4-5 Sequential Circuit Design
Design Procedure
Finding State Diagrams and State Tables
4-6 Designing with D Flip-Flops
Designing with Unused States
4-7 Designing with JK Flip-Flops
Flip-Flop Excitation Tables
Design Procedure
4-8 HDL Representation for Sequential Circuits -- VHDL
4-9 HDL Representation for Sequential Circuits -- Verilog
4-10 References
Problems
CHAPTER 5 249
REGISTERS AND COLJNTERS
5-1 Definition of Register and Counter
5-2 Registers
Register with Parallel Load
5-3 Shift Registers
Serial Transfer
Serial Addition
Shift Register with Parallel Load
Bidirectional Shift Register
5-4 Ripple Counter
5-5 Synchronous Binary Counters
Design of Binary Counters
Counter with D Flip-Flops
Serial and Parallel Counters
Up-Down Binary Counter
Binary Counter with Parallel Load
5-6 Other Counters
BCD Counter
Arbitrary Count Sequence
5-7 HDL Representation for Shift Registers and Counters
5-8 HDL Representation for Shift Registers and Counters
5-9 Chapter Sununary
References
Problems
CHAPTER 6 285
MEMORY AND PROGRAMMABLE LOGIC DEVICES
6-1 Memory and Progranunable Logic Device
Definitions
6-2 Random-access Memory
Write and Read Operations
Timing Waveforms
Properties of Memory
6-3 RAM Integrated Circuits
Three-State Buffers
Coincident Selection
Dynamic RAM ICs
6-4 Array of RAM ICs
Arrays of Dynamic RAM ICs
6-5 Programmable Logic Technologies
6-6 Read--only Memory
Combinational Circuit Implementation
6-7 Programmable Logic Array
6-8 Programmable Array Logic Devices
6-9 VLSI Programmable Logic Devices
Altera MAX 7000 CPLDs
Xilinx XC4000 Structure
Xilinx Interconnections
Xilinx Logic
6-10 Chapter Sununary
References
Problems
CHAPTER 7 339
REGISTER TRANSFERS AND DATAPATHS
7-1 Datapaths and Operations
7-2 Register Transfer Operations
A Note For VHDL And Verilog Users Only
7-3 Microoperations
Arithmetic Microoperations
Logic Microoperations
Shift Microoperations
7-4 Multiplexer-based Transfer
7-5 Bus-based Transfer
Three-State Bus
Memory Transfer
7-6 Datapaths
7-7 The Arithmetic/Logic Unit
Anthmetic Circuit
Logic Circuit
Arithmetic/Logic Unit
7-8 The Shifter
Barrel Shifter
7-9 Datapath Representation
7-10 The Control Word
7-11 Pipelined Datapath
Execution of Pipeline Microoperations
7-12 Chapter Sununary
References
Problems
CHAPTER 8 391
SEQUENCING AND CONTOL
8-1 The Control Unit
8-2 Algorithmic State Machines
The ASM Chart
Timing Considerations
8-3 Design Example: Binary Multiplier
Binary Multiplier
Multiplier Datapath
ASM Chart for Multiplier
8-4 Hardwired Control
Sequence Register and Decoder
One Flip-Flop per State
8-5 HDL Representation of the Binary Multiplier - VHDL
8-6 HDL Representation of the Binary Multiplier - Verilog
8-7 Microprogranund Control
Binary Multiplier Example
8-8 A Simple Computer Architecture
Instructions
Instruction Formats
Storage Resource Diagram
8-9 Single-Cycle Hardwired Control
Instruction Decoder
Sample Instructions and Program
8-10 Multiple-Cycle Microprogranund Control
Microprogram Design
The Hardwired Alternative
8-11 Pipelined Control
Pipeline Programming and Performance
8-12 Chapter Summary
References
Problems
CHAPTER 9 467
INSTRUCTION SET ARCHITECTURE
9-1 Computer Architecture Concepts
Basic Computer Operation Cycle
Register Set
9-2 Operand Addressing
Three-address Instructions
Two-address Insmictions
One-address Instructions
Zero-address Instructions
Addressing Architectures
9-3 Addressing Modes
Implied Mode
Inundiate Mode
Register and Register-Indirect Modes
Direct Addressing Mode
Indirect Addressing Mode
Relative Addressing Mode
Indexed Addressing Mode
Summary of Addressing Modes
9-4 Insmiction Set Architectures
9-5 Data Transfer Instructions
Stack Instructions
Independent versus Memory-Mapped I/O
9-6 Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
9-7 Floating-point Computations
Arithmetic Operations
Biased Exponent
Standard Operand Format
9-8 Program Control Instructions
Conditional Branch Instructions
Procedure Call and Return Instructions
9-9 Program Interrupt
Types of Interrupts
Processing External Interrupts
9-10 Chapter Sununary
References
Problems
CHAPTER l0 511
CENTRAL PROCESSING UNIT DESIGNS
10-1 Two CPU Designs
10-2 The Complex Instruction Set Computer
Insmiction Set Aichitecture
Datapath Organization
Microprogranuned Control Organization
Microprograrn Structure
Microroutines
10-3 The Reduced Instruction Set Computer
Instruction Set Architecture
Addressing Modes
Datapath Organization
Control Organization
Data Hazards
Control Hazards
10-4 More on Design
CISC-RISC Comparison
High-Performance CPU Concepts
Recent Architectural Innovations
Digital Systems
10-5 Chapter Summary
References
Problems
CHAPTER ll 575
INPUT-OUTPUT AND COMMUNICATION
11-1 Computer llO
11-2 Sample Peripherals
Keyboard
Hard Disk
Gmphics Display
I/O Transfer Rates
11-3 I/O Interfaces
I/O Bus and Interface Unit
Example of I/O Interface
Strobing
Handshaking
11-4 Serial Communicahon
Asynchronous Transmission
Synchronous Transmission
The Keyboard Revisited
A Packet-Based Serial I/O Bus
11-5 Modes of Transfer
Example of Program-Controlled Thosfer
Interrupt-Initiated Transfer
11-6 Priority Interrupt
Daisy Chain Priority
Parallel Priority Hardware
11-7 Direct Memory Access
DMA Controller
DMA Transfer
11-8 I/O Processors
11-9 Chapter Summary
References
Prob1ems
CHAPTER l2 613
MEMOR SYSTEMS
12-1 Memory Hierarchy
12-2 Locality of Reference
12-3 Cache Memory
Cache Mappings
Line Size
Cache Loading
Write Methods
Integration of Concepts
Instruction and Data Caches
Multiple-Level Caches
12-4 Virtual Memory
Page Tables
Translation Lookaside Buffer
Vinual Memory and Cache
12-5 Chapter Sununary
References
Problems
INDEX 643
DIGlTAL COMPUTERS AND INFORMATION
1-1 Digital Computers
Information Representation
Computer Structure
More on the Generic Computer
1-2 Number Systems
Binary Numbers
Octal and Hexadecimal Numbers
Number Ranges
1-3 Arithmetic Operations
Conversion from Decimal to Other Bases
1-4 Decimal Codes
BCD Addition
1-5 Alphanumeric Codes
ASCII Character Code
Parity Bit
1-6 Chapter Sununary
References
Problems
CHAPTER 2 27
COMBINATIONAL LOGIC CIRCUITS
2-1 Binary Logic and Gates
Binary Logic
Logic Gates
2-2 Boolean Algebra
Basic Identities of Boolean Algebra
Algebraic Manipulation
Complement of a Function
2-3 Standard Forms
Minterms and Maxterms
Sum of Products
Product of Sums
2-4 Map Simplification
Two-Variable Map
Me-Variable Map
Four-Variable Map
2-5 Map Manipulation
Essential Prime Implicants
Nonessential Prime Implicants
Product-of Sums Simplification
Don't--Care Condihons
2-6 NAND and NOR Gates
NAND Circuits
Two-Level Implementation
Multi1evel NAND Circuits
NOR Circuits
2-7 Exclusive-OR Gates
Odd Function
Parity Generation and Checking
2-8 Integrated Circuits
Levels of Integration
Digital Logic Families
Positive and Negative Logic
Transmission Gates
2-9 Chapter Sununary
References
Problems
CHAPTER 3
COMBINATIONAL LOGIC DESIGN
3-1 Combinational Circuits
3-2 Design Topics
Design Hierarchy
Top-Down Design
Computer-Aided Design
Hardware Description Languages
Logic Synthesis
3-3 Analysis Procedure
Derivation of Boolean Functions
Derivation of the Truth Table
Logic Simulation
3-4 Design Procedure
Code Converters
3-5 Decoders
Decoder Expansion
Combinahonal Circuit Implemenation
3-6 Enceders
Priority Encoder
3-7 Multiplexers
Combinahonal Circuit Implementation
Demultiplexer
3-8 Binare Adders
Half Adder
Full Adder
Binare Ripple Carry Adder
Cap Lookahead Aduer
3-9 Binary Subtraction
Complements
Subtraction with Complements
3-10 Binary Adder-Subtractors
Signed Binary Numbers
Signed Binary Addition and Subtraction
Overflow
3-11 Binny Multipliers
3-12 Decimal Arithmetic
Use of Complements in Decimal
3-13 HDL Representations -- VHDL
Structural Description
Dataflow Description
Hierarchical Description
Behavioral Description
3-14 HDL Representations - Verilog
Structural Description
Dataflow Description
Hierarchical Description
Behavioral Description
3-15 Chapter Sununary
References
Problems
CHAPTER 4 183
SEQUENTIAL CIRCUITS
4-1 Sequential Circuit Definitions
4-2 Latches
SR and S R Latches
D Latch
4-3 Flip-Flops
Master-Slave Flip-Flop
Edge-Triggered Flip-Flop
Standard Graphics Symbols
Characteristic Tables
Direct Inputs
4-4 Sequential Circuit Analysis
Input Equations
State Table
Analysis with JK Flip-Flops
State Diagram
4-5 Sequential Circuit Design
Design Procedure
Finding State Diagrams and State Tables
4-6 Designing with D Flip-Flops
Designing with Unused States
4-7 Designing with JK Flip-Flops
Flip-Flop Excitation Tables
Design Procedure
4-8 HDL Representation for Sequential Circuits -- VHDL
4-9 HDL Representation for Sequential Circuits -- Verilog
4-10 References
Problems
CHAPTER 5 249
REGISTERS AND COLJNTERS
5-1 Definition of Register and Counter
5-2 Registers
Register with Parallel Load
5-3 Shift Registers
Serial Transfer
Serial Addition
Shift Register with Parallel Load
Bidirectional Shift Register
5-4 Ripple Counter
5-5 Synchronous Binary Counters
Design of Binary Counters
Counter with D Flip-Flops
Serial and Parallel Counters
Up-Down Binary Counter
Binary Counter with Parallel Load
5-6 Other Counters
BCD Counter
Arbitrary Count Sequence
5-7 HDL Representation for Shift Registers and Counters
5-8 HDL Representation for Shift Registers and Counters
5-9 Chapter Sununary
References
Problems
CHAPTER 6 285
MEMORY AND PROGRAMMABLE LOGIC DEVICES
6-1 Memory and Progranunable Logic Device
Definitions
6-2 Random-access Memory
Write and Read Operations
Timing Waveforms
Properties of Memory
6-3 RAM Integrated Circuits
Three-State Buffers
Coincident Selection
Dynamic RAM ICs
6-4 Array of RAM ICs
Arrays of Dynamic RAM ICs
6-5 Programmable Logic Technologies
6-6 Read--only Memory
Combinational Circuit Implementation
6-7 Programmable Logic Array
6-8 Programmable Array Logic Devices
6-9 VLSI Programmable Logic Devices
Altera MAX 7000 CPLDs
Xilinx XC4000 Structure
Xilinx Interconnections
Xilinx Logic
6-10 Chapter Sununary
References
Problems
CHAPTER 7 339
REGISTER TRANSFERS AND DATAPATHS
7-1 Datapaths and Operations
7-2 Register Transfer Operations
A Note For VHDL And Verilog Users Only
7-3 Microoperations
Arithmetic Microoperations
Logic Microoperations
Shift Microoperations
7-4 Multiplexer-based Transfer
7-5 Bus-based Transfer
Three-State Bus
Memory Transfer
7-6 Datapaths
7-7 The Arithmetic/Logic Unit
Anthmetic Circuit
Logic Circuit
Arithmetic/Logic Unit
7-8 The Shifter
Barrel Shifter
7-9 Datapath Representation
7-10 The Control Word
7-11 Pipelined Datapath
Execution of Pipeline Microoperations
7-12 Chapter Sununary
References
Problems
CHAPTER 8 391
SEQUENCING AND CONTOL
8-1 The Control Unit
8-2 Algorithmic State Machines
The ASM Chart
Timing Considerations
8-3 Design Example: Binary Multiplier
Binary Multiplier
Multiplier Datapath
ASM Chart for Multiplier
8-4 Hardwired Control
Sequence Register and Decoder
One Flip-Flop per State
8-5 HDL Representation of the Binary Multiplier - VHDL
8-6 HDL Representation of the Binary Multiplier - Verilog
8-7 Microprogranund Control
Binary Multiplier Example
8-8 A Simple Computer Architecture
Instructions
Instruction Formats
Storage Resource Diagram
8-9 Single-Cycle Hardwired Control
Instruction Decoder
Sample Instructions and Program
8-10 Multiple-Cycle Microprogranund Control
Microprogram Design
The Hardwired Alternative
8-11 Pipelined Control
Pipeline Programming and Performance
8-12 Chapter Summary
References
Problems
CHAPTER 9 467
INSTRUCTION SET ARCHITECTURE
9-1 Computer Architecture Concepts
Basic Computer Operation Cycle
Register Set
9-2 Operand Addressing
Three-address Instructions
Two-address Insmictions
One-address Instructions
Zero-address Instructions
Addressing Architectures
9-3 Addressing Modes
Implied Mode
Inundiate Mode
Register and Register-Indirect Modes
Direct Addressing Mode
Indirect Addressing Mode
Relative Addressing Mode
Indexed Addressing Mode
Summary of Addressing Modes
9-4 Insmiction Set Architectures
9-5 Data Transfer Instructions
Stack Instructions
Independent versus Memory-Mapped I/O
9-6 Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
9-7 Floating-point Computations
Arithmetic Operations
Biased Exponent
Standard Operand Format
9-8 Program Control Instructions
Conditional Branch Instructions
Procedure Call and Return Instructions
9-9 Program Interrupt
Types of Interrupts
Processing External Interrupts
9-10 Chapter Sununary
References
Problems
CHAPTER l0 511
CENTRAL PROCESSING UNIT DESIGNS
10-1 Two CPU Designs
10-2 The Complex Instruction Set Computer
Insmiction Set Aichitecture
Datapath Organization
Microprogranuned Control Organization
Microprograrn Structure
Microroutines
10-3 The Reduced Instruction Set Computer
Instruction Set Architecture
Addressing Modes
Datapath Organization
Control Organization
Data Hazards
Control Hazards
10-4 More on Design
CISC-RISC Comparison
High-Performance CPU Concepts
Recent Architectural Innovations
Digital Systems
10-5 Chapter Summary
References
Problems
CHAPTER ll 575
INPUT-OUTPUT AND COMMUNICATION
11-1 Computer llO
11-2 Sample Peripherals
Keyboard
Hard Disk
Gmphics Display
I/O Transfer Rates
11-3 I/O Interfaces
I/O Bus and Interface Unit
Example of I/O Interface
Strobing
Handshaking
11-4 Serial Communicahon
Asynchronous Transmission
Synchronous Transmission
The Keyboard Revisited
A Packet-Based Serial I/O Bus
11-5 Modes of Transfer
Example of Program-Controlled Thosfer
Interrupt-Initiated Transfer
11-6 Priority Interrupt
Daisy Chain Priority
Parallel Priority Hardware
11-7 Direct Memory Access
DMA Controller
DMA Transfer
11-8 I/O Processors
11-9 Chapter Summary
References
Prob1ems
CHAPTER l2 613
MEMOR SYSTEMS
12-1 Memory Hierarchy
12-2 Locality of Reference
12-3 Cache Memory
Cache Mappings
Line Size
Cache Loading
Write Methods
Integration of Concepts
Instruction and Data Caches
Multiple-Level Caches
12-4 Virtual Memory
Page Tables
Translation Lookaside Buffer
Vinual Memory and Cache
12-5 Chapter Sununary
References
Problems
INDEX 643
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