书籍详情
正确硬件设计与验证方法
作者：Tiziana Margaria 著
出版社：湖南文艺出版社
出版时间：2001-12-01
ISBN：9783540425410
定价：¥654.84
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内容简介
This book constitutes the refereed proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods， CHARME 2001， held in Livingston， Scotland， UK in September 2001.The 28 revised full papers and eight short papers presented together with two invited papers and one special paper were carefully reviewed and selected from 56 submissions. The book offers topical sections on model checking， clocking issues， theorem proving with higher order logics， hardware compilation， tools， component verification， case studies， algorithm verification， and duration calculus.
作者简介
暂缺《正确硬件设计与验证方法》作者简介
目录
Invited Contributions
View from the Fringe of the Fringe (Extended Summary)
Hardware Synthesis Using SAFL and Application to Processor Design(Invited Talk)
FMCAD 2OOO
Applications of Hierarchical Verification in Model Checking
Model Checking 1
Pruning Techniques for the SAT-Based Bounded Model Checking Problem
Heuristics for Hierarchical Partitioning with Application to Model Checking
Short Papers 1
Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs
Deriving Real-Time Programs from Duration Calculus Specifications
Reproducing Synchronization Bugs with Model Checking
Formally-Based Design Evaluation
Clocking Issues
Multiclock Esterel
Register Transformations with Multiple Clock Domains
Temporal Properties of Self-Timed Rings
Short Papers 2
Coverability Analysis Using Symbolic Model Checking
Specifying Hardware Timing with ET-LoTOS
Formal Pipeline Design
Verification of Basic Block Schedules Using RTL Transformations
Joint Session with TPHOLs
Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking
Proof Engineering in the Large: Formal Verification of Pentium@ 4 Floating-Point Divider
Hardware Compilation
Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques
A Higher-Level Language for Hardware Synthesis
Tools
Model Checking 2
Component Verification
Case Studies
Algorithm Verification
Duration Calculus
Author Index
View from the Fringe of the Fringe (Extended Summary)
Hardware Synthesis Using SAFL and Application to Processor Design(Invited Talk)
FMCAD 2OOO
Applications of Hierarchical Verification in Model Checking
Model Checking 1
Pruning Techniques for the SAT-Based Bounded Model Checking Problem
Heuristics for Hierarchical Partitioning with Application to Model Checking
Short Papers 1
Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs
Deriving Real-Time Programs from Duration Calculus Specifications
Reproducing Synchronization Bugs with Model Checking
Formally-Based Design Evaluation
Clocking Issues
Multiclock Esterel
Register Transformations with Multiple Clock Domains
Temporal Properties of Self-Timed Rings
Short Papers 2
Coverability Analysis Using Symbolic Model Checking
Specifying Hardware Timing with ET-LoTOS
Formal Pipeline Design
Verification of Basic Block Schedules Using RTL Transformations
Joint Session with TPHOLs
Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking
Proof Engineering in the Large: Formal Verification of Pentium@ 4 Floating-Point Divider
Hardware Compilation
Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques
A Higher-Level Language for Hardware Synthesis
Tools
Model Checking 2
Component Verification
Case Studies
Algorithm Verification
Duration Calculus
Author Index
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