书籍详情
数字设计和计算机体系结构
作者：（美）David Money Harris、等 著
出版社：机械工业出版社
出版时间：2008-01-01
ISBN：9787111223931
定价：¥65.00
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内容简介
《数字设计和计算机体系结构（英文版）》采用了一种独特的现代数字设计方法，先介绍数字逻辑门，接着讲述组合电路和时序电路的设计，并以这些基本的数字逻辑设计概念为基础。重点介绍如何设计实际的MIPS处理器。另外，在全书的实例中运用Verilog和VHDL展示基于CAD的电路设计方法和技术。通过《数字设计和计算机体系结构（英文版）》，读者能够构建自己的微处理器，并能够自顶向下地理解微处理器的工作原理。《数字设计和计算机体系结构（英文版）》基于作者丰富的教学和实践经验，以幽默的写作风格展示了最新的数字设计方法。
作者简介
David Money Harris 哈维玛德学院工程学副教授。他曾经为英特尔、惠普、SUN等公司设计微处理器。Sarah L.Harris 哈维玛德学院工程学副教授。她在斯坦福大学获得电子工程博士学位，擅长计算机体系结构设计和系统设计。
目录
Preface
Features
Online Supplements
How to Use the Software Tools in a Course
Labs
Bugs
Acknowledgments
Chapter I From Zero to One
1.1 The Game Plan
1.2 The Art of Managing Complexity
1.2.1 Abstraction
1.2.2 Discipline
1.2.3 The Three - Y's
1.3 The Digital Abstraction
1.4 Number Systems
1.4.1 Decimal Numbers
1.4.2 Binary Numbers
1.4.3 Hexadecimal Numbers
1.4.4 Bytes, Nibbles, and All That Jazz
1.4.5 Binary Addition
1.4.6 Signed Binary Numbers
1.5 Logic Gates
1.5.1 NOT Gate
1.5.2 Buffer
1.5.3 AND Gate
1.5.4 OR Gate
1.5.5 Other Two-Input Gates
1.5.6 Multiple-Input Gates
1.6 Beneath the Digital Abstraction
1.6.1 Supply Voltage
1.6.2 Logic Levels
1.6.3 Noise Margins
1.6.4 DC Transfer Characteristics
1.6.5 The Static Discipline
1.7 CMOS Transistors
1.7.1 Semiconductors
1.7.2 Diodes
1.7.3 Capacitors
1.7.4 CMOS and pMOS Transistors
1.7.5 CMOS NOT Gate
1.7.6 Other CMOS Logic Gates
1.7.7 Transmission Gates
1.7.8 Pseudo-nMOS Logic
1.8 Power Consumption
1.9 Summary and a Look Ahead
Exercises
Interview Questions
Chapter 2 ComMnational Logic
2.1 Introduction
2.2 Boolean Equations
2.2.1 Terminology
2.2.2 Sum-of-Products Form
2.2.3 Product-of-Sums Form
2.3 Boolean Algebra
2.3.1 Axioms
2.3.2 Theorems of One Variable
2.3.3 Theorems of Several Variables
2.3.4 The Truth Behind It All
2.3.5 Simplifying Equations
2.4 From Logic to Gates
2.5 Multilevel Combinational Logic
2.5.1 Hardware Reduction
2.5.2 Bubble Pushing
2.6 X's and Z's, Oh My
2.6.1 Illegal Value: X
2.6.2 Floating Value: Z
2.7 Karnaugh Maps
2.7.1 Circular Thinking
2.7.2 Logic Minimization with K-Maps
2.7.3 Don't Cares
2.7.4 The Big Picture
2.8 Combinational Building Blocks
2.8.1 Multiplexers
2.8.2 Decoders
2.9 Timing
2.9.1 Propagation and Contamination Delay
2.9.2 Glitcbes
2.10 Summary
Exercises
Interview Questions
Chapter3 Sequential Logic Design
Chapter4 Hardware Description Languages
Chapter5 Digital Building Blocks
Chapter6 Architecture
Chapter7 Microarchitecture
Chapter8 Memory Systems
Appendix A Digital System Implementation
Appendix B MIPS Instructions
Further Reading
Index
Features
Online Supplements
How to Use the Software Tools in a Course
Labs
Bugs
Acknowledgments
Chapter I From Zero to One
1.1 The Game Plan
1.2 The Art of Managing Complexity
1.2.1 Abstraction
1.2.2 Discipline
1.2.3 The Three - Y's
1.3 The Digital Abstraction
1.4 Number Systems
1.4.1 Decimal Numbers
1.4.2 Binary Numbers
1.4.3 Hexadecimal Numbers
1.4.4 Bytes, Nibbles, and All That Jazz
1.4.5 Binary Addition
1.4.6 Signed Binary Numbers
1.5 Logic Gates
1.5.1 NOT Gate
1.5.2 Buffer
1.5.3 AND Gate
1.5.4 OR Gate
1.5.5 Other Two-Input Gates
1.5.6 Multiple-Input Gates
1.6 Beneath the Digital Abstraction
1.6.1 Supply Voltage
1.6.2 Logic Levels
1.6.3 Noise Margins
1.6.4 DC Transfer Characteristics
1.6.5 The Static Discipline
1.7 CMOS Transistors
1.7.1 Semiconductors
1.7.2 Diodes
1.7.3 Capacitors
1.7.4 CMOS and pMOS Transistors
1.7.5 CMOS NOT Gate
1.7.6 Other CMOS Logic Gates
1.7.7 Transmission Gates
1.7.8 Pseudo-nMOS Logic
1.8 Power Consumption
1.9 Summary and a Look Ahead
Exercises
Interview Questions
Chapter 2 ComMnational Logic
2.1 Introduction
2.2 Boolean Equations
2.2.1 Terminology
2.2.2 Sum-of-Products Form
2.2.3 Product-of-Sums Form
2.3 Boolean Algebra
2.3.1 Axioms
2.3.2 Theorems of One Variable
2.3.3 Theorems of Several Variables
2.3.4 The Truth Behind It All
2.3.5 Simplifying Equations
2.4 From Logic to Gates
2.5 Multilevel Combinational Logic
2.5.1 Hardware Reduction
2.5.2 Bubble Pushing
2.6 X's and Z's, Oh My
2.6.1 Illegal Value: X
2.6.2 Floating Value: Z
2.7 Karnaugh Maps
2.7.1 Circular Thinking
2.7.2 Logic Minimization with K-Maps
2.7.3 Don't Cares
2.7.4 The Big Picture
2.8 Combinational Building Blocks
2.8.1 Multiplexers
2.8.2 Decoders
2.9 Timing
2.9.1 Propagation and Contamination Delay
2.9.2 Glitcbes
2.10 Summary
Exercises
Interview Questions
Chapter3 Sequential Logic Design
Chapter4 Hardware Description Languages
Chapter5 Digital Building Blocks
Chapter6 Architecture
Chapter7 Microarchitecture
Chapter8 Memory Systems
Appendix A Digital System Implementation
Appendix B MIPS Instructions
Further Reading
Index
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