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80*86 IBM PC及兼容计算机汇编语言，设计与接口技术（卷I和卷II 第3版 英文影印版）
作者：Muhammad Ali Mazidi,Janice Gillispie Mazidi
出版社：清华大学出版社
出版时间：2002-06-01
ISBN：9787302049999
定价：¥85.00
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内容简介
由于PC机的大量应用，有关PC机软、硬件设计的基础知识在大专院校广为传授。本书可作为有关专业课程的教科书。全面内容涵盖了从8088到Pentium Pro全部*86微处理机。作者系统全面地介绍了微机的软、硬件设计。全书包括两大部分：1）泯编语言程序设计；2）IBM PC机接口设计。在介绍汇编语言程序的章节中，以编程方法为引导，逐步加入各种语句及指令，有很多实例，又结合程序调试方法，与PC机的BIOS及DOS编辑结合得好。在接口设计方面，从PC机应用的芯片到设备，从电路设计到编程都进行了详细的阐述。在一些应用举例中，与PC机本身资源结合得好。书中专有一章讨论ISA，PCI和USB总线。全书实例、解答题丰富，有利于读者深入理解。本书附带软盘一张。
作者简介
暂缺《80*86 IBM PC及兼容计算机汇编语言，设计与接口技术（卷I和卷II 第3版 英文影印版）》作者简介
目录
PREFACE TO THE SERIES
PREFACE TO VOLUMES I AND II
CHAPTER 0: INTRODUCTION TO COMPUTING
SECTION 0.1: NUMBERING AND CODING SYSTEMS
SECTION 0.2: INSIDE THE COMPUTER
SECTION 0.3: BRIEF HISTORY OF THE CPU
CHAPTER 1: THE 80x86 MICROPROCESSOR
SECTION 1.1: BRIEF HISTORY OF THE 80x86 FAMILY
SECTION 1.2: INSIDE THE 8088/8086
SECTION 1.3: INTRODUCTION TO ASSEMBLY PROGRAMMING
SECTION 1.4: INTRODUCTION TO PROGRAM SEGMENTS
SECTION 1.5: MORE ABOUT SEGMENTS IN THE 80x86
SECTION 1.6: 80x86 ADDRESSING MODES
CHAPTER 2: ASSEMBLY LANGUAGE PROGRAMMING
SECTION 2.1: DIRECTIVES AND A SAMPLE PROGRAM
SECTION 2.2: ASSEMBLE, UNK, AND RUN A PROGRAM
SECTION 2.3: MORE SAMPLE PROGRAMS
SECTION 2.4: CONTROL TRANSFER INSTRUCTIONS
SECTION 2.5: DATA TYPES AND DATA DEFINITION
SECTION 2.6: FULL SEGMENT DEFINITION
SECTION 2.7: EXE VS. COM FILES
CHAPTER 3: ARITHMETIC AND LOGIC INSTRUCTIONS AND PROGRAMS
SECTION 3.1: UNSIGNED ADDITION AND SUBTRACTION
SECTION 3.2: UNSIGNED MULTIPLICATION AND DIWSION
SECTION 3.3: LOGIC INSTRUCTIONS AND SAMPLE PROGRAMS
SECTION 3.4: BCD AND ASCII OPERANDS AND INSTRUCTIONS
SECTION 3.5: ROTATE INSTRUCTIONS
SECTION 3.6: BITWISE OPERATION IN THE C LANGUAGE
CHAPTER 4: BIOS AND DOS PROGRAMMING IN ASSEMBLY AND C
SECTION 4.1: BIOS INT 10H PROGRAMMING
SECTION 4.2: DOS INTERRUPT 21H
SECTION 4.3: INT 16H KEYBOARD PROGRAMMING
SECTION 4.4: INTERRUPT PROGRAMMING WITH C
CHAPTER 5: MACROS AND THE MOUSE
SECTION 5.1: WHAT IS A MACRO AND HOW IS IT USED?
SECTION 5.2: MOUSE PROGRAMMING WITH INTERRUPT 33H
CHAPTER 6: SIGNED NUMBERS, STRINGS, AND TABLES
SECTION 6.1: SIGNED NUMBER ARITHMETIC OPERATIONS
SECTION 6.2: STRING AND TABLE OPERATIONS
CHAPTER 7: MODULES; MODULAR AND C PROGRAMMING
SECTION 7.1: WRITING AND UNKING MODULES
SECTION 7.2: SOME VERY USEFUL MODULES
SECTION 7.3: PASSING PARAMETERS AMONG MODULES
SECTION 7.4: COMBINING ASSEMBLY LANGUAGE AND C PROGRAMS
CHAPTER 8: 32-BIT PROGRAMMING FOR 386 AND 486 MACHINES
SECTION 8.1: 803B6/80486 MACHINES IN REAL MODE
SECTION 8.2: SOME SIMPLE 38/486 PROGRAMS
SECTION 8.3: 80x86 PERFORMANCE COMPARISON
CHAPTER 9: 8088/86 MICROPROCESSORS AND SUPPORTING CHIPS
SECTION 9.1: OVERVIEW OF INTELS 80X86 MICROPROCESSORS
SECTION 9.2: 8088/8086 MICROPROCESSOR
SECTION 9.3: 8284 CLOCK GENERATOR AND DRIVER
SECTION 9.4: 8288 BUS CONTROLLER
SECTION 9.5: IBM PCIXT BUSES
CHAPTER 10: 80286 MICROPROCESSOR AND SUPPORTING CHIPS
SECTION 10.1: 80286 MICROPROCESSOR
SECTION 10.2: 822B4 CLOCK GENERATOR
SECTION 10.3: 82288 BUS CONTROLLER
SECTION 10.4: 80286 IN IBM PC AT AND ISA BUSES
CHAPTER 11: MEMORY AND MEMORY INTERFACING
SECTION 11.1: SEMICONDUCTOR MEMORY FUNDAMENTALS
SECTION 11.2: IBM PC MEMORY MAP
SECTION 11.3: MEMORY INTERFACING IN 8088 IBM PCIXT
SECTION 11.4: 8088/86 READ AND WRITE CYCLE TIME SPECIFICATIONS
SECTION 11.5: 80286/386SX MEMORY INTERFACING AND TIMING
SECTION 11.6: MEMORY BUS BANDWIDTH FOR 80x86 COMPUTERS
CHAPTER 12: I/O, 8255 AND DEVICE INTERFACING
SECTION 12.1: INPUT/OUTPUT INSTRUCTIONS IN THE 808S/86
SECTION 12.2: IIO DESIGN IN THE 808/86
SECTION 12.3: 8255 PROGRAMMABLE PERIPHERAL INTERFACING
SECTION 12.4: IBM PC, PS I/O MAP
SECTION 12.5: 80286 AT COMPUTERS AND ISA BUS IIO PORTS
SECTION 12.6: INTERFACING I/O TO PCIXT AT PS, AND ISA COMPUTERS
SECTION 12.7: PC INTERFACE TRAINER AND PC BUS EXTENDER
SECTION 12.8: INTERFACING AN LCD TO THE PC
SECTION 12.9: INTERFACING A STEPPER MOTOR TO A PC
SECTION 12.10: INTERFACING DAC TO A PC
SECTION 12.11: INTERFACING ADC AND SENSORS TO A PC
SECTION 12.12: I/O PROGRAMMING WITH C
CHAPTER 13: 82S3/54 TIMER AND MUSIC
SECTION 13.1: 8253/54 TIMER DESCRIPTION AND INITIALIZADON
SECTION 13.2: IBM PC 8253/54 TIMER CONNECTIONS AND PROGRAMMING
SECTION 13.3: GENERATING MUSIC ON THE IBM PC
SECTION 13.4: SHAPE Of 8253/54 OUTPUTS
CHAPTER 14: INTERRUPTS AND THE 8259 CHIP
SECTION 14.1: 8088/86 INTERRUPTS
SECTION 14.2: IBM PC AND MS DOS ASSIGNMENT OF INTERRUPTS
SECTION 14.3: 8259 PROGRAMMABLE INTERRUPT CONTROLLER
SECTION 14.4: USE OF THE 8259 CHIP IN THE ISM PC/XT
SECTION 14.5: INTERRUPTS ON 80286 AND HIGHER 80X86 PCs
CHAPTER 15: DIRECT MEMORY ACCESSING; THE 8237 DMA CHIP
SECTION 15.2: 8237 DMA CHIP PROGRAMMING
SECTION 15.3: 8237 DMA INTERFACING IN THE IBM PC/XT
SECTION 15.4: REFRESHING DRAM USING CHANNEL 0 OF THE 8237
SECTION 15.5: DMA IN 80x86-BASED PC ATTYPE COMPUTERS
CHAPTER 16: VIDEO AND VIDEO ADAPTERS
SECTION 16.1: PRINCIPLES OF MONITORS AND VIDEO ADAPTERS
SECTION 16.2: VIDEO ADAPTERS AND TEXT MODE PROGRAMMING
SECTION 16.3: TEXT MODE PROGRAMMING USING INT 10H
SECTION 16.4: GRAPHICS AND GRAPHICS PROGRAMMING
CHAPTER 17: SERIAL DATA COMMUNICATION AND THE 16450/8250/51 CHIPS
SECTION 17.1: BASICS OF SERIAL COMMUNICATION
SECTION 17.2: ACCESSING I8M PC COM PORTS USING DOS AND BIOS
SECTION 17.3: INTERFACING THE NS8250l1 6450 UART IN THE IBM PC
SECTION 17.4: INTEL 8251 USART AND SYNCHRONOUS COMMUNICATION
CHAPTER 18: KEYBOARD AND PRINTER INTERFACING
SECTION 18.1: INTERFACING THE KEYBOARD TO THE CPU
SECTION 18.2: PC KEYBOARD INTERFACING AND PROGRAMMING
SECTION 18.3: PRINTER AND PRINTER INTERFACING IN THE IBM PC
SECTION 18.4: BIDIRECTIONAL DATA BUS IN PARALLEL PORTS
CHAPTER 19: FLOPPY DISKS, HARD DISKS, AND FILES
SECTION 19.1: FLOPPY DISK ORGANIZTION
SECTION 19.2: HARD DISKS
SECTION 19.3: DISK FILE PROGRAMMING
CHAPTER 20: THE 80x87 MATH COPROCESSOR
SECTION 20.1: MATH COPROCESSOR AND IEEE FLOADNG-POINT STANDARDS
SECTION 20.2: 80x87 INSTRUCTIONS AND PROGRAMMING
SECTION 20.3: 8087 HARDWARE CONNECTIONS IN THE IBM PC/XT
SECTION 20.4: 80x87 INSTRUCTIONS AND TMING
CHAPTER 21: 386 MICROPROCESSOR: REAL vs. PROTECTED MODE
SECTION 21.1: 80386 IN REAL MODE
SECTION 21.2: 80386: A HARDWARE VIEW
SECTION 21.3: 80386 PROTECTED MODE
CHAPTER 22: HIGH-SPEED MEMORY INTERFACING AND CACHE
SECTION 22.1: MEMORY CYCLE TIME OF THE 80X86
SECTION 22.2: PAGE, STATIC COLUMN, AND NIBBLE MODE DRAMS
SECTION 22.3: CACHE MEMORY
SECTION 22.4: EDO, SDRAM, AND RAMBUS MEMORIES
CHAPTER 23: 486, PENTIUM, PENTIUM PRO AND MMX
SECTION 23.1: THE 80486 MICROPROCESSOR
SECTION 23.2: INTELS PENTIUM
SECTION 23.3: RISC ARCHITECTURE
SECTION 23.4: PENTIUM PRO PROCESSOR
SECTION 23.5: MMX TECHNOLOGY
SECTION 23.6: PROCESSOR IDENTIFICATION IN INTEL X86
CHAPTER 24: MS DOS STRUCTURE, TSR, AND DEVICE DRIVERS
SECTION 24.1: MS DOS STRUCTURE
SECTION 24.2: TSR AND DEVICE DRIVERS
CHAPTER 25: MS DOS MEMORY MANAGEMENT
SECTION 25.1: 80x86 PC MEMORY TERMINOLOGY AND CONCEPTS
SECTION 25.2: DOS MEMORY MANAGEMENT AND LOADING HIGH
CHAPTER 26: IC TECHNOLOGY AND SYSTEM DESIGN CONSIDERATIONS
SECTION 26.1: OVERVIEW OF IC TECHNOLOGY
SECTION 26.2: IC INTERFACING AND SYSTEM DESIGN CONSIDERATIONS
SECTION 26.3: DATA INTEGRITY AND ERROR DETECTION IN DRAM
CHAPTER 27: ISA, PCI, AND USB BUSES
SECTION 27.1: ISA BUSES
SECTION 27.2: PCI LOCAL BUSES
SECTION 27.3: USB PORT
CHAPTER 28: PROGRAMMING DOS, BIOS, & HARDWARE WITH C/C++
SECTION 28.1: BIOS & DOS INTERRUPT PROGRAMMING WITH C
SECTION 28.2: PROGRAMMING PC HARDWARE WITH C/C++
APPENOIX A: DEBUG PROGRAMMING
APPENOIX B: 80x86 INSTRUCTIONS AND TIMING
APPENDIX C: ASSEMBLER DIRECTIVES AND NAMING RULES
APPENDIX D: DOS INTERRUPT 21H AND 33H LISTING
APPENOIX E: BIOS INTERRUPTS
APPENDIX F: ASCII CODES
APPENDIX G: IIO ADDRESS MAPS
APPENDIX H: ISM PCIPS BIOS DATA AREA
APPENDIX I: DATA SHEETS
REFERENCES
INDEX
PREFACE TO VOLUMES I AND II
CHAPTER 0: INTRODUCTION TO COMPUTING
SECTION 0.1: NUMBERING AND CODING SYSTEMS
SECTION 0.2: INSIDE THE COMPUTER
SECTION 0.3: BRIEF HISTORY OF THE CPU
CHAPTER 1: THE 80x86 MICROPROCESSOR
SECTION 1.1: BRIEF HISTORY OF THE 80x86 FAMILY
SECTION 1.2: INSIDE THE 8088/8086
SECTION 1.3: INTRODUCTION TO ASSEMBLY PROGRAMMING
SECTION 1.4: INTRODUCTION TO PROGRAM SEGMENTS
SECTION 1.5: MORE ABOUT SEGMENTS IN THE 80x86
SECTION 1.6: 80x86 ADDRESSING MODES
CHAPTER 2: ASSEMBLY LANGUAGE PROGRAMMING
SECTION 2.1: DIRECTIVES AND A SAMPLE PROGRAM
SECTION 2.2: ASSEMBLE, UNK, AND RUN A PROGRAM
SECTION 2.3: MORE SAMPLE PROGRAMS
SECTION 2.4: CONTROL TRANSFER INSTRUCTIONS
SECTION 2.5: DATA TYPES AND DATA DEFINITION
SECTION 2.6: FULL SEGMENT DEFINITION
SECTION 2.7: EXE VS. COM FILES
CHAPTER 3: ARITHMETIC AND LOGIC INSTRUCTIONS AND PROGRAMS
SECTION 3.1: UNSIGNED ADDITION AND SUBTRACTION
SECTION 3.2: UNSIGNED MULTIPLICATION AND DIWSION
SECTION 3.3: LOGIC INSTRUCTIONS AND SAMPLE PROGRAMS
SECTION 3.4: BCD AND ASCII OPERANDS AND INSTRUCTIONS
SECTION 3.5: ROTATE INSTRUCTIONS
SECTION 3.6: BITWISE OPERATION IN THE C LANGUAGE
CHAPTER 4: BIOS AND DOS PROGRAMMING IN ASSEMBLY AND C
SECTION 4.1: BIOS INT 10H PROGRAMMING
SECTION 4.2: DOS INTERRUPT 21H
SECTION 4.3: INT 16H KEYBOARD PROGRAMMING
SECTION 4.4: INTERRUPT PROGRAMMING WITH C
CHAPTER 5: MACROS AND THE MOUSE
SECTION 5.1: WHAT IS A MACRO AND HOW IS IT USED?
SECTION 5.2: MOUSE PROGRAMMING WITH INTERRUPT 33H
CHAPTER 6: SIGNED NUMBERS, STRINGS, AND TABLES
SECTION 6.1: SIGNED NUMBER ARITHMETIC OPERATIONS
SECTION 6.2: STRING AND TABLE OPERATIONS
CHAPTER 7: MODULES; MODULAR AND C PROGRAMMING
SECTION 7.1: WRITING AND UNKING MODULES
SECTION 7.2: SOME VERY USEFUL MODULES
SECTION 7.3: PASSING PARAMETERS AMONG MODULES
SECTION 7.4: COMBINING ASSEMBLY LANGUAGE AND C PROGRAMS
CHAPTER 8: 32-BIT PROGRAMMING FOR 386 AND 486 MACHINES
SECTION 8.1: 803B6/80486 MACHINES IN REAL MODE
SECTION 8.2: SOME SIMPLE 38/486 PROGRAMS
SECTION 8.3: 80x86 PERFORMANCE COMPARISON
CHAPTER 9: 8088/86 MICROPROCESSORS AND SUPPORTING CHIPS
SECTION 9.1: OVERVIEW OF INTELS 80X86 MICROPROCESSORS
SECTION 9.2: 8088/8086 MICROPROCESSOR
SECTION 9.3: 8284 CLOCK GENERATOR AND DRIVER
SECTION 9.4: 8288 BUS CONTROLLER
SECTION 9.5: IBM PCIXT BUSES
CHAPTER 10: 80286 MICROPROCESSOR AND SUPPORTING CHIPS
SECTION 10.1: 80286 MICROPROCESSOR
SECTION 10.2: 822B4 CLOCK GENERATOR
SECTION 10.3: 82288 BUS CONTROLLER
SECTION 10.4: 80286 IN IBM PC AT AND ISA BUSES
CHAPTER 11: MEMORY AND MEMORY INTERFACING
SECTION 11.1: SEMICONDUCTOR MEMORY FUNDAMENTALS
SECTION 11.2: IBM PC MEMORY MAP
SECTION 11.3: MEMORY INTERFACING IN 8088 IBM PCIXT
SECTION 11.4: 8088/86 READ AND WRITE CYCLE TIME SPECIFICATIONS
SECTION 11.5: 80286/386SX MEMORY INTERFACING AND TIMING
SECTION 11.6: MEMORY BUS BANDWIDTH FOR 80x86 COMPUTERS
CHAPTER 12: I/O, 8255 AND DEVICE INTERFACING
SECTION 12.1: INPUT/OUTPUT INSTRUCTIONS IN THE 808S/86
SECTION 12.2: IIO DESIGN IN THE 808/86
SECTION 12.3: 8255 PROGRAMMABLE PERIPHERAL INTERFACING
SECTION 12.4: IBM PC, PS I/O MAP
SECTION 12.5: 80286 AT COMPUTERS AND ISA BUS IIO PORTS
SECTION 12.6: INTERFACING I/O TO PCIXT AT PS, AND ISA COMPUTERS
SECTION 12.7: PC INTERFACE TRAINER AND PC BUS EXTENDER
SECTION 12.8: INTERFACING AN LCD TO THE PC
SECTION 12.9: INTERFACING A STEPPER MOTOR TO A PC
SECTION 12.10: INTERFACING DAC TO A PC
SECTION 12.11: INTERFACING ADC AND SENSORS TO A PC
SECTION 12.12: I/O PROGRAMMING WITH C
CHAPTER 13: 82S3/54 TIMER AND MUSIC
SECTION 13.1: 8253/54 TIMER DESCRIPTION AND INITIALIZADON
SECTION 13.2: IBM PC 8253/54 TIMER CONNECTIONS AND PROGRAMMING
SECTION 13.3: GENERATING MUSIC ON THE IBM PC
SECTION 13.4: SHAPE Of 8253/54 OUTPUTS
CHAPTER 14: INTERRUPTS AND THE 8259 CHIP
SECTION 14.1: 8088/86 INTERRUPTS
SECTION 14.2: IBM PC AND MS DOS ASSIGNMENT OF INTERRUPTS
SECTION 14.3: 8259 PROGRAMMABLE INTERRUPT CONTROLLER
SECTION 14.4: USE OF THE 8259 CHIP IN THE ISM PC/XT
SECTION 14.5: INTERRUPTS ON 80286 AND HIGHER 80X86 PCs
CHAPTER 15: DIRECT MEMORY ACCESSING; THE 8237 DMA CHIP
SECTION 15.2: 8237 DMA CHIP PROGRAMMING
SECTION 15.3: 8237 DMA INTERFACING IN THE IBM PC/XT
SECTION 15.4: REFRESHING DRAM USING CHANNEL 0 OF THE 8237
SECTION 15.5: DMA IN 80x86-BASED PC ATTYPE COMPUTERS
CHAPTER 16: VIDEO AND VIDEO ADAPTERS
SECTION 16.1: PRINCIPLES OF MONITORS AND VIDEO ADAPTERS
SECTION 16.2: VIDEO ADAPTERS AND TEXT MODE PROGRAMMING
SECTION 16.3: TEXT MODE PROGRAMMING USING INT 10H
SECTION 16.4: GRAPHICS AND GRAPHICS PROGRAMMING
CHAPTER 17: SERIAL DATA COMMUNICATION AND THE 16450/8250/51 CHIPS
SECTION 17.1: BASICS OF SERIAL COMMUNICATION
SECTION 17.2: ACCESSING I8M PC COM PORTS USING DOS AND BIOS
SECTION 17.3: INTERFACING THE NS8250l1 6450 UART IN THE IBM PC
SECTION 17.4: INTEL 8251 USART AND SYNCHRONOUS COMMUNICATION
CHAPTER 18: KEYBOARD AND PRINTER INTERFACING
SECTION 18.1: INTERFACING THE KEYBOARD TO THE CPU
SECTION 18.2: PC KEYBOARD INTERFACING AND PROGRAMMING
SECTION 18.3: PRINTER AND PRINTER INTERFACING IN THE IBM PC
SECTION 18.4: BIDIRECTIONAL DATA BUS IN PARALLEL PORTS
CHAPTER 19: FLOPPY DISKS, HARD DISKS, AND FILES
SECTION 19.1: FLOPPY DISK ORGANIZTION
SECTION 19.2: HARD DISKS
SECTION 19.3: DISK FILE PROGRAMMING
CHAPTER 20: THE 80x87 MATH COPROCESSOR
SECTION 20.1: MATH COPROCESSOR AND IEEE FLOADNG-POINT STANDARDS
SECTION 20.2: 80x87 INSTRUCTIONS AND PROGRAMMING
SECTION 20.3: 8087 HARDWARE CONNECTIONS IN THE IBM PC/XT
SECTION 20.4: 80x87 INSTRUCTIONS AND TMING
CHAPTER 21: 386 MICROPROCESSOR: REAL vs. PROTECTED MODE
SECTION 21.1: 80386 IN REAL MODE
SECTION 21.2: 80386: A HARDWARE VIEW
SECTION 21.3: 80386 PROTECTED MODE
CHAPTER 22: HIGH-SPEED MEMORY INTERFACING AND CACHE
SECTION 22.1: MEMORY CYCLE TIME OF THE 80X86
SECTION 22.2: PAGE, STATIC COLUMN, AND NIBBLE MODE DRAMS
SECTION 22.3: CACHE MEMORY
SECTION 22.4: EDO, SDRAM, AND RAMBUS MEMORIES
CHAPTER 23: 486, PENTIUM, PENTIUM PRO AND MMX
SECTION 23.1: THE 80486 MICROPROCESSOR
SECTION 23.2: INTELS PENTIUM
SECTION 23.3: RISC ARCHITECTURE
SECTION 23.4: PENTIUM PRO PROCESSOR
SECTION 23.5: MMX TECHNOLOGY
SECTION 23.6: PROCESSOR IDENTIFICATION IN INTEL X86
CHAPTER 24: MS DOS STRUCTURE, TSR, AND DEVICE DRIVERS
SECTION 24.1: MS DOS STRUCTURE
SECTION 24.2: TSR AND DEVICE DRIVERS
CHAPTER 25: MS DOS MEMORY MANAGEMENT
SECTION 25.1: 80x86 PC MEMORY TERMINOLOGY AND CONCEPTS
SECTION 25.2: DOS MEMORY MANAGEMENT AND LOADING HIGH
CHAPTER 26: IC TECHNOLOGY AND SYSTEM DESIGN CONSIDERATIONS
SECTION 26.1: OVERVIEW OF IC TECHNOLOGY
SECTION 26.2: IC INTERFACING AND SYSTEM DESIGN CONSIDERATIONS
SECTION 26.3: DATA INTEGRITY AND ERROR DETECTION IN DRAM
CHAPTER 27: ISA, PCI, AND USB BUSES
SECTION 27.1: ISA BUSES
SECTION 27.2: PCI LOCAL BUSES
SECTION 27.3: USB PORT
CHAPTER 28: PROGRAMMING DOS, BIOS, & HARDWARE WITH C/C++
SECTION 28.1: BIOS & DOS INTERRUPT PROGRAMMING WITH C
SECTION 28.2: PROGRAMMING PC HARDWARE WITH C/C++
APPENOIX A: DEBUG PROGRAMMING
APPENOIX B: 80x86 INSTRUCTIONS AND TIMING
APPENDIX C: ASSEMBLER DIRECTIVES AND NAMING RULES
APPENDIX D: DOS INTERRUPT 21H AND 33H LISTING
APPENOIX E: BIOS INTERRUPTS
APPENDIX F: ASCII CODES
APPENDIX G: IIO ADDRESS MAPS
APPENDIX H: ISM PCIPS BIOS DATA AREA
APPENDIX I: DATA SHEETS
REFERENCES
INDEX
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