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模拟电路版图的艺术（影印版）
作者：（ ）Alan Hastings著
出版社：清华大学出版社
出版时间：2004-04-01
ISBN：9787302082262
定价：¥72.00
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内容简介
查看“微电子类教材”专题本书是第一本有关模拟版图设计的教科书，内容全面，实践性强，是作者三十余年研究、设计实践经验的积累和总结。本书涉及了模拟集成电路设计中的3种工艺：标准双极工艺、CMOS硅栅工艺和BiCMOS工艺，通过这些介绍，读者可以容易地了解其他新的工艺。本书阐述了版图设计中许多非常重要的方面，例如故障机制中的ESD和闩锁、匹配原理、器件的联合、保护环以及高压器件等，对许多实际问题都给出了解决方案；另外对于版图设计的一些背景知识也给予了非常简明易懂的介绍，包括器件物理、工艺、故障模型等。本书的主要特点是：（1）实用性强，基于作者丰富的实践经验，本书讨论了许多鲜为人知的机制和效应，介绍了目前业界最前沿的知识和技术；（2）易读易懂，本书的数学内容极少，读者只要具备基本代数和基础电子学的知识就可以读懂；（3）为方便读者，书中包括了许多有用的背景知识；（4）为理解器件运行（operation），作者提出了一个直观模型carrier-basedmodel来代替传统的component-basedmodel；（5）本书还提供了大量的习题，读者可以通过设计软件来完成，也可以直接计算完成。
作者简介
暂缺《模拟电路版图的艺术（影印版）》作者简介
目录
Preface
Acknowledgments
1 Device Physics
1.1 Semiconductors 1
1.1.1 Generation and Recombination 4
1.1.2 Extrinsic Semiconductors 6
1.1.3 Diffusion and Drift 9
1.2 PN Junctions 10
1.2.1 Depletion Regions 10
1.2.2 PN Diodes 13
1.2.3 SchottkyDiodes 15
1.2.4 Zener Diodes 17
1.2.5 Ohmic Contacts 19
1.3 Bipolar Junction Transistors 20
1.3.1 Beta 22
1.3.2 I-V Characteristics 23
1.4 MOS Transistors 24
1.4.1 Threshold Voltage 27
1.4.2 I-V Characteristics 29
1.5 JFET Transistors 31
1.6 Summary 33
1.7 Exercises 34
2 Semiconductor Fabrication
2.1 Silicon Manufacture 36
2.1.1 Crystal Growth 37
2.1.2 Wafer Manufacturing 38
2.1.3 The Crystal Structure of Silicon 38
2.2 Photolithography 40
2.2.1 Photoresists 40
2.2.2 Photomasks and Reticles 41
2.2.3 Patterning 42
2.3 Oxide Growth and Removal 42
2.3.1 Oxide Growth and Deposition 43
2.3.2 Oxide Removal 44
2.3.3 Other Effects of Oxide Growth and Removal 46
2.3.4 Local Oxidation of Silicon (LOCOS) 48
2.4 Diffusion and Ion Implantation 49
2.4.1 Diffusion 50
2.4.2 Other Effects of Diffusion 52
2.4.3 Ion Implantation 53
2.5 Silicon Deposition 55
2.5.1 Epitaxy 56
2.5.2 Polysilicon Deposition 58
2.6 Metallization 58
2.6.1 Deposition and Removal of Aluminum 59
2.6.2 Refractory Barrier Metal 60
2.6.3 Silicidation 62
2.6.4 Interlevel Oxide, Interlevel Nitride, and Protective Overcoat 63
2.7 Assembly 64
2.7.1 Mount and Bond 66
2.7.2 Packaging 69
2.8 Summary 69
2.9 Exercises 69
3 Representative Processes
3.1 Standard Bipolar 72
3.1.1 Essential Features 72
3.1.2 Fabrication Sequence 73
3.1.3 Available Devices 77
3.1.4 Process Extensions 84
3.2 Polysilicon-Gate CMOS 87
3.2.1 Essential Features 88
3.2.2 Fabrication Sequence 89
3.2.3 Available Devices 95
3.2.4 Process Extensions 100
3.3 Analog BiCMOS 104
3.3.1 Essential Features 104
3.3.2 Fabrication Sequence 106
3.3.3 Available Devices 111
3.4 Summary 115
3.5 Exercises 116
4 Failure Mechanisms
4.1 Electrical Overstress 118
4.1.1 Electrostatic Discharge (ESD) 118
4.1.2 Electromigration 121
4.1.3 The Antenna Effect 122
4.2 Contamination 124
4.2.1 Dry Corrosion 124
4.2.2 Mobile Ion Contamination 125
4.3 Surface Effects 128
4.3.1 Hot Carrier Injection 128
4.3.2 Parasitic Channels and Charge Spreading 131
4.4 Parasitics 139
4.4.1 Substrate Debiasing 140
4.4.2 Minority-Carrier Injection 143
4.5 Summary 153
4.6 Exercises 153
5 Resistors
5.1 Resistivity and Sheet Resistance 156
5.2 Resistor Layout 158
5.3 Resistor Variability 162
5.3.1 Process Variation 162
5.3.2 Temperature Variation 163
5.3.3 Nonlinearity 163
5.3.4 Contact Resistance 166
5.4 Resistor Parasitics 167
5.5 Comparison of Available Resistors 170
5.5.1 Base Resistors 170
5.5.2 Emitter Resistors 171
5.5.3 Base Pinch Resistors 172
5.5.4 High-Sheet Resistors 173
5.5.5 Epi Pinch Resistors 175
5.5.6 Metal Resistors 176
5.5.7 Poly Resistors 177
5.5.8 NSD and PSD Resistors 180
5.5.9 N-well Resistors 180
5.5.10 Thin-film Resistors 181
5.6 Adjusting ResistorValues 182
5.6.1Tweaking Resistors 182
5.6.2 Trimming Resistors 185
5.7 Summary 191
5.8 Exercises 192
6 Capacitors
6.1 Capacitance 194
6.2 Capacitor Variability 200
6.2.1 Process Variation 200
6.2.2Voltage Modulation and Temperature Variation 201
6.3 Capacitor Parasitics 203
6.4 Comparison of Available Capacitors 205
6.4.1Base-emitter Junction Capacitors 205
6.4.2 MOS Capacitors 207
6.4.3 Poly-poly Capacitors 209
6.4.4 Miscellaneous Styles of Capacitors 211
6.5 Summary 212
6.6 Exercises 212
7 Matching of Resistors and Capacitors
7.1 Measuring Mismatch 214
7.2 Causes of Mismatch 217
7.2.1Random Statistical Fluctuations 217
7.2.2Process Biases 219
7.2.3 Pattern Shift 220
7.2.4Variations in Polysilicon Etch Rate 222
7.2.5Diffusion Interactions 224
7.2.6Stress Gradients and Package Shifts 226
7.2.7Temperature Gradients and Thermoelectrics 236
7.2.8Electrostatic Interactions 242
7.3 Rules for Device Matching 249
7.3.1Rules for Resistor Matching 249
7.3.2Rules for Capacitor Matching 253
7.4 Summary 257
7.5 Exercises 257
8 Bipolar Transistors
8.1 Topics in Bipolar Transistor Operation 260
8.1.1 BetaRolloff 262
8.1.2 Avalanche Breakdown 262
8.1.3 Thermal Runaway and Secondary Breakdown 264
8.1.4 Saturation in NPN Transistors 266
8.1.5 Saturation in Lateral PNP Transistors 270
8.1.6 Parasitics of Bipolar Transistors 272
8.2 Standard Bipolar Small-signal Transistors 274
8.2.1 The Standard Bipolar NPN Transistor 274
8.2.2 The Standard Bipolar Substrate PNP Transistor 279
8.2.3 The Standard Bipolar Lateral PNP Transistor 283
8.2.4 High-voltage Bipolar Transistors 291
8.3 Alternative Small-signal Bipolar Transistors 293
8.3.1 Extensions to Standard Bipolar 293
8.3.2 Analog BiCMOS Bipolar Transistors 294
8.3.3 Bipolar Transistors in a CMOS Process 297
8.3.4 Advanced-technology Bipolar Transistors 299
8.4 Summary 302
8.5 Exercises 303
9 Applications of Bipolar Transistors
9.1 Power Bipolar Transistors 306
9.1.1 Failure Mechanisms of NPN Power Transistors 307
9.1.2 Layout of Power NPN Transistors 311
9.1.3 Saturation Detection and Limiting 319
9.2 Matching Bipolar Transistors 322
9.2.1 Random Variations 323
9.2.2 Emitter Degeneration 325
9.2.3 NBLShadow 327
9.2.4 Thermal Gradients 328
9.2.5 Stress Gradients 332
9.3 Rules for Bipolar Transistor Matching 334
9.3.1 Rules for Matching NPN Transistors 335
9.3.2 Rules for Matching Lateral PNP Transistors 337
9.4 Summary 340
9.5 Exercises 340
10 Diodes
10.1 Diodes in Standard Bipolar 343
10.1.1 Diode-connected Transistors 343
10.1.2 Zener Diodes 346
10.1.3 Schottky Diodes 352
10.2 Diodes in CMOS and BiCMOS Processes 356
10.3 Matching Diodes 359
10.3.1 Matching PN Junction Diodes 359
10.3.2 Matching Zener Diodes 360
10.3.3 Matching Schottky Diodes 361
10.4 Summary 362
10.5 Exercises 362
11 MOS Transistors
11.1 Topics in MOS Transistor Operation 364
11.1.1 Modeling the MOS Transistor 364
11.1.2 Parasitics of MOS Transistors 370
11.2 Self-aligned Poly-Gate CMOS Transistors 376
11.2.1 Coding the MOS Transistor 377
11.2.2 N-well and P-well Processes 379
11.2.3 Channel Stops 381
11.2.4 Threshold Adjustlmplants 383
11.2.5 Scaling the Transistor 386
11.2.6 Variant Structures 388
11.2.7 Backgate Contacts 393
11.3 Summary 396
11.4 Exercises 396
12 Applications of MOS Transistors
12.1 Extended-voltage Transistors 399
12.1.1 LDD and DDD Transistors 400
12.1.2 Extended-drain Transistors 403
12.1.3 Multiple Gate Oxides 405
12.2 Power MOS Transistors 407
12.2.1 Conventional MOS Power Transistors 410
12.2.2 DMOS Transistors 417
12.3 The JFET Transistor 422
12.3.1 Modeling the JFET 422
12.3.2 JFET Layout 423
12.4 MOS Transistor Matching 426
12.4.1 Geometric Effects 427
12.4.2 Diffusion and Etch Effects 430
12.4.3 Thermal and Stress Effects 433
12.4.4 Common-centroid Layout of MOS Transistors 435
12.5 Rules for MOS Transistor Matching 439
12.6 Summary 442
12.7 Exercises 443
13 Special Topics
13.1 Merged Devices 445
13.1.1 Flawed Device Mergers 446
13.1.2 Successful Device Mergers 450
13.1.3 Low-risk Merged Devices 452
13.1.4 Medium-risk Merged Devices 453
13.1.5 Devising New Merged Devices 455
13.2 Guard Rings 455
13.2.1 Standard Bipolar Electron Guard Rings 456
13.2.2 Standard Bipolar Hole Guard Rings 457
13.2.3 Guard Rings in CMOS and BiCMOS Designs 458
13.3 Single-level Interconnection 460
13.3.1 Mock Layouts and Stick Diagrams 461
13.3.2 Techniques for Crossing Leads 463
13.3.3 Types of Tunnels 464
13.4 Constructing the Padring 466
13.4.1 Scribe Streets and Alignment Markers 466
13.4.2 Bondpads, Trimpads, and Testpads 468
13.4.3 ESD Structures 471
13.4.4 SelectingESD Structures 483
13.5 Exercises 485
14 Assembling the Die
14.1 Die Planning 488
14.1.1 Cell Area Estimation 489
14.1.2 Die Area Estimation 491
14.1.3 Gross Profit Margin 494
14.2 Floorplanning 495
14.3 Top-level Interconnection 500
14.3.1 Principles of Channel Routing 501
14.3.2 Special Routing Techniques 503
14.3.3 Electromigration 506
14.3.4 Minimizing Stress Effects 508
14.4 Conclusion 510
14.5 Exercises 510
Appendices
A. Table of Acronyms Used in the Text 513
B. The Miller Indices of a Cubic Crystal 516
C. Sample Layout Rules 519
D. Mathematical Derivations 527
E. Sources for Layout Editor Software 532
Index 533
Acknowledgments
1 Device Physics
1.1 Semiconductors 1
1.1.1 Generation and Recombination 4
1.1.2 Extrinsic Semiconductors 6
1.1.3 Diffusion and Drift 9
1.2 PN Junctions 10
1.2.1 Depletion Regions 10
1.2.2 PN Diodes 13
1.2.3 SchottkyDiodes 15
1.2.4 Zener Diodes 17
1.2.5 Ohmic Contacts 19
1.3 Bipolar Junction Transistors 20
1.3.1 Beta 22
1.3.2 I-V Characteristics 23
1.4 MOS Transistors 24
1.4.1 Threshold Voltage 27
1.4.2 I-V Characteristics 29
1.5 JFET Transistors 31
1.6 Summary 33
1.7 Exercises 34
2 Semiconductor Fabrication
2.1 Silicon Manufacture 36
2.1.1 Crystal Growth 37
2.1.2 Wafer Manufacturing 38
2.1.3 The Crystal Structure of Silicon 38
2.2 Photolithography 40
2.2.1 Photoresists 40
2.2.2 Photomasks and Reticles 41
2.2.3 Patterning 42
2.3 Oxide Growth and Removal 42
2.3.1 Oxide Growth and Deposition 43
2.3.2 Oxide Removal 44
2.3.3 Other Effects of Oxide Growth and Removal 46
2.3.4 Local Oxidation of Silicon (LOCOS) 48
2.4 Diffusion and Ion Implantation 49
2.4.1 Diffusion 50
2.4.2 Other Effects of Diffusion 52
2.4.3 Ion Implantation 53
2.5 Silicon Deposition 55
2.5.1 Epitaxy 56
2.5.2 Polysilicon Deposition 58
2.6 Metallization 58
2.6.1 Deposition and Removal of Aluminum 59
2.6.2 Refractory Barrier Metal 60
2.6.3 Silicidation 62
2.6.4 Interlevel Oxide, Interlevel Nitride, and Protective Overcoat 63
2.7 Assembly 64
2.7.1 Mount and Bond 66
2.7.2 Packaging 69
2.8 Summary 69
2.9 Exercises 69
3 Representative Processes
3.1 Standard Bipolar 72
3.1.1 Essential Features 72
3.1.2 Fabrication Sequence 73
3.1.3 Available Devices 77
3.1.4 Process Extensions 84
3.2 Polysilicon-Gate CMOS 87
3.2.1 Essential Features 88
3.2.2 Fabrication Sequence 89
3.2.3 Available Devices 95
3.2.4 Process Extensions 100
3.3 Analog BiCMOS 104
3.3.1 Essential Features 104
3.3.2 Fabrication Sequence 106
3.3.3 Available Devices 111
3.4 Summary 115
3.5 Exercises 116
4 Failure Mechanisms
4.1 Electrical Overstress 118
4.1.1 Electrostatic Discharge (ESD) 118
4.1.2 Electromigration 121
4.1.3 The Antenna Effect 122
4.2 Contamination 124
4.2.1 Dry Corrosion 124
4.2.2 Mobile Ion Contamination 125
4.3 Surface Effects 128
4.3.1 Hot Carrier Injection 128
4.3.2 Parasitic Channels and Charge Spreading 131
4.4 Parasitics 139
4.4.1 Substrate Debiasing 140
4.4.2 Minority-Carrier Injection 143
4.5 Summary 153
4.6 Exercises 153
5 Resistors
5.1 Resistivity and Sheet Resistance 156
5.2 Resistor Layout 158
5.3 Resistor Variability 162
5.3.1 Process Variation 162
5.3.2 Temperature Variation 163
5.3.3 Nonlinearity 163
5.3.4 Contact Resistance 166
5.4 Resistor Parasitics 167
5.5 Comparison of Available Resistors 170
5.5.1 Base Resistors 170
5.5.2 Emitter Resistors 171
5.5.3 Base Pinch Resistors 172
5.5.4 High-Sheet Resistors 173
5.5.5 Epi Pinch Resistors 175
5.5.6 Metal Resistors 176
5.5.7 Poly Resistors 177
5.5.8 NSD and PSD Resistors 180
5.5.9 N-well Resistors 180
5.5.10 Thin-film Resistors 181
5.6 Adjusting ResistorValues 182
5.6.1Tweaking Resistors 182
5.6.2 Trimming Resistors 185
5.7 Summary 191
5.8 Exercises 192
6 Capacitors
6.1 Capacitance 194
6.2 Capacitor Variability 200
6.2.1 Process Variation 200
6.2.2Voltage Modulation and Temperature Variation 201
6.3 Capacitor Parasitics 203
6.4 Comparison of Available Capacitors 205
6.4.1Base-emitter Junction Capacitors 205
6.4.2 MOS Capacitors 207
6.4.3 Poly-poly Capacitors 209
6.4.4 Miscellaneous Styles of Capacitors 211
6.5 Summary 212
6.6 Exercises 212
7 Matching of Resistors and Capacitors
7.1 Measuring Mismatch 214
7.2 Causes of Mismatch 217
7.2.1Random Statistical Fluctuations 217
7.2.2Process Biases 219
7.2.3 Pattern Shift 220
7.2.4Variations in Polysilicon Etch Rate 222
7.2.5Diffusion Interactions 224
7.2.6Stress Gradients and Package Shifts 226
7.2.7Temperature Gradients and Thermoelectrics 236
7.2.8Electrostatic Interactions 242
7.3 Rules for Device Matching 249
7.3.1Rules for Resistor Matching 249
7.3.2Rules for Capacitor Matching 253
7.4 Summary 257
7.5 Exercises 257
8 Bipolar Transistors
8.1 Topics in Bipolar Transistor Operation 260
8.1.1 BetaRolloff 262
8.1.2 Avalanche Breakdown 262
8.1.3 Thermal Runaway and Secondary Breakdown 264
8.1.4 Saturation in NPN Transistors 266
8.1.5 Saturation in Lateral PNP Transistors 270
8.1.6 Parasitics of Bipolar Transistors 272
8.2 Standard Bipolar Small-signal Transistors 274
8.2.1 The Standard Bipolar NPN Transistor 274
8.2.2 The Standard Bipolar Substrate PNP Transistor 279
8.2.3 The Standard Bipolar Lateral PNP Transistor 283
8.2.4 High-voltage Bipolar Transistors 291
8.3 Alternative Small-signal Bipolar Transistors 293
8.3.1 Extensions to Standard Bipolar 293
8.3.2 Analog BiCMOS Bipolar Transistors 294
8.3.3 Bipolar Transistors in a CMOS Process 297
8.3.4 Advanced-technology Bipolar Transistors 299
8.4 Summary 302
8.5 Exercises 303
9 Applications of Bipolar Transistors
9.1 Power Bipolar Transistors 306
9.1.1 Failure Mechanisms of NPN Power Transistors 307
9.1.2 Layout of Power NPN Transistors 311
9.1.3 Saturation Detection and Limiting 319
9.2 Matching Bipolar Transistors 322
9.2.1 Random Variations 323
9.2.2 Emitter Degeneration 325
9.2.3 NBLShadow 327
9.2.4 Thermal Gradients 328
9.2.5 Stress Gradients 332
9.3 Rules for Bipolar Transistor Matching 334
9.3.1 Rules for Matching NPN Transistors 335
9.3.2 Rules for Matching Lateral PNP Transistors 337
9.4 Summary 340
9.5 Exercises 340
10 Diodes
10.1 Diodes in Standard Bipolar 343
10.1.1 Diode-connected Transistors 343
10.1.2 Zener Diodes 346
10.1.3 Schottky Diodes 352
10.2 Diodes in CMOS and BiCMOS Processes 356
10.3 Matching Diodes 359
10.3.1 Matching PN Junction Diodes 359
10.3.2 Matching Zener Diodes 360
10.3.3 Matching Schottky Diodes 361
10.4 Summary 362
10.5 Exercises 362
11 MOS Transistors
11.1 Topics in MOS Transistor Operation 364
11.1.1 Modeling the MOS Transistor 364
11.1.2 Parasitics of MOS Transistors 370
11.2 Self-aligned Poly-Gate CMOS Transistors 376
11.2.1 Coding the MOS Transistor 377
11.2.2 N-well and P-well Processes 379
11.2.3 Channel Stops 381
11.2.4 Threshold Adjustlmplants 383
11.2.5 Scaling the Transistor 386
11.2.6 Variant Structures 388
11.2.7 Backgate Contacts 393
11.3 Summary 396
11.4 Exercises 396
12 Applications of MOS Transistors
12.1 Extended-voltage Transistors 399
12.1.1 LDD and DDD Transistors 400
12.1.2 Extended-drain Transistors 403
12.1.3 Multiple Gate Oxides 405
12.2 Power MOS Transistors 407
12.2.1 Conventional MOS Power Transistors 410
12.2.2 DMOS Transistors 417
12.3 The JFET Transistor 422
12.3.1 Modeling the JFET 422
12.3.2 JFET Layout 423
12.4 MOS Transistor Matching 426
12.4.1 Geometric Effects 427
12.4.2 Diffusion and Etch Effects 430
12.4.3 Thermal and Stress Effects 433
12.4.4 Common-centroid Layout of MOS Transistors 435
12.5 Rules for MOS Transistor Matching 439
12.6 Summary 442
12.7 Exercises 443
13 Special Topics
13.1 Merged Devices 445
13.1.1 Flawed Device Mergers 446
13.1.2 Successful Device Mergers 450
13.1.3 Low-risk Merged Devices 452
13.1.4 Medium-risk Merged Devices 453
13.1.5 Devising New Merged Devices 455
13.2 Guard Rings 455
13.2.1 Standard Bipolar Electron Guard Rings 456
13.2.2 Standard Bipolar Hole Guard Rings 457
13.2.3 Guard Rings in CMOS and BiCMOS Designs 458
13.3 Single-level Interconnection 460
13.3.1 Mock Layouts and Stick Diagrams 461
13.3.2 Techniques for Crossing Leads 463
13.3.3 Types of Tunnels 464
13.4 Constructing the Padring 466
13.4.1 Scribe Streets and Alignment Markers 466
13.4.2 Bondpads, Trimpads, and Testpads 468
13.4.3 ESD Structures 471
13.4.4 SelectingESD Structures 483
13.5 Exercises 485
14 Assembling the Die
14.1 Die Planning 488
14.1.1 Cell Area Estimation 489
14.1.2 Die Area Estimation 491
14.1.3 Gross Profit Margin 494
14.2 Floorplanning 495
14.3 Top-level Interconnection 500
14.3.1 Principles of Channel Routing 501
14.3.2 Special Routing Techniques 503
14.3.3 Electromigration 506
14.3.4 Minimizing Stress Effects 508
14.4 Conclusion 510
14.5 Exercises 510
Appendices
A. Table of Acronyms Used in the Text 513
B. The Miller Indices of a Cubic Crystal 516
C. Sample Layout Rules 519
D. Mathematical Derivations 527
E. Sources for Layout Editor Software 532
Index 533
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