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数字集成电路：设计透视 英文版
作者：（ ）Jan M.Rabaey等著
出版社：清华大学出版社
出版时间：2004-03-01
ISBN：9787302079682
定价：¥68.00
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内容简介
微电子技术是信息科学技术的核心技术之一，微电子产业是当代高新技术产业群的核 心和维护国家主权、保障国家安全的战略性产业。我国在《信息产业“十五”计划纲要》中明确提出：坚持自主发展，增强创新能力和核心竞争力，掌握以集成电路和软件技术为重点的信息产业的核心技术，提高具有自主知识产权产品的比重。发展集成电路技术的关键之一是培养具有国际竞争力的专业人才。 微电子技术发展迅速，内容更新快，而我国微电子专业图书数量少，且内容和体系不能反映科技发展的水平，不能满足培养人才的需求，为此，我们系统挑选了—…批国外经典教材和前沿著作，组织分批出版。图书选择的几个基本原则是：在本领域内广泛采用，有很大影响力：内容反映科技的最新发展，所述内容是本领域的研究热点；编写和体系与国内现有图书差别较大，能对我国微电子教育改革有所启示。本套丛书还侧重于微电子技术的实用性，选取了一批集成电路设计方面的工程技术用书，使读者能方便地应用于实践。本套丛书不仅能作为相关课程的教科书和教学参考书，也可作为工程技术人员的自学读物。
作者简介
暂缺《数字集成电路：设计透视 英文版》作者简介
目录
Preface
Part 1 The Fabrics
Chapter 1 Introduction
1.1 A Historical Perspective
1.2 Issues in Digital Integrated Circuit Design
1.3 Quality Metrics of a Digital Design
1.3.1 Cost of an Integrated Circuit
1.3.2 Functionality and Robustness
1.3.3 Performance
1.3.4 Power and Energy Consumption
1.4 Summary
1.5 To Probe Further
Reference Books
References
Chapter 2 The Manufacturing Process
2.1 Introduction
2.2 Manufacturing CMOS Integrated Circuits
2.2.1 The Silicon Wafer
2.2.2 Photolithography
2.2.3 Some Recurring Process Steps
2.2.4 Simplified CMOS Process Flow
2.3 Design Rules-The Contract between Designer and Process Engineer
2.4 Packaging Integrated Circuits
2.4.1 Package Materials
2.4.2 Interconnect Levels
2.4.3 Thermal Considerations in Packaging
2.5 Perspective--Trends in Process Technology
2.5.1 Short-Term Developments
2.5.2 In the Longer Term
2.6 Summary
2.7 To Probe Further
References
Design Methodology Insert A IC LAYOUT
A.1 To Probe Further
References
Chapter 3 The Devices
3.1 Introduction
3.2 The Diode
3.2.1 A First Glance at the Diode--The Depletion Region
3.2.2 Static Behavior
3.2.3 Dynamic, or Transient, Behavior
3.2.4 The Actual Diode--Secondary Effects
3.2.5 The SPICE Diode Model
3.3 The MOS(FET) Transistor
3.3.1 A First Glance at the Device
3.3.2 The MOS Transistor under Static Conditions
3.3.3 The Actual MOS Transistor---Some Secondary Effects
3.3.4 SPICE Models for the MOS Transistor
3.4 A Word on Process Variations
3.5 Perspective--Technology Scaling
3.6 Summary
3.7 To Probe Further
References
Design Methodology Insert B Circuit Simulation
References
Chapter 4 The Wire
4.1 Introduction
4.2 A First Glance
4.3 Interconnect Parameters--Capacitance, Resistance, and Inductance
4.3.1 Capacitance
4.3.2 Resistance
4.3.3 Inductance
4.4 Electrical Wire Models
4.4.1 The Ideal Wire
4.4.2 The Lumped Model
4.4.3 The Lumped RC Model
4.4.4 The Distributed rc Line
4.4.5 The Transmission Line
SPICE Wire Models
4.5.1 Distributed rc Lines in SPICE
4.5.2 Transmission Line Models in SPICE
4.5.3 Perspective: A Look into the Future
4.6 Summary
4.7 To Probe Further
References
Part 2 A Circuit Perspective
Chapter 5 The CMOS Inverter
5.1 Introduction
5.2 The Static CMOS Inverter--An Intuitive Perspective
5.3 Evaluating the Robustness of the CMOS Inverter: The Static Behavior
5.3.1 Switching Threshold
5.3.2 Noise Margins
5.3.3 Robustness Revisited
5.4 Performance of CMOS Inverter: The Dynamic Behavior
5.4.1 Computing the Capacitances
5.4.2 Propagation Delay: First-Order Analysis
5.4.3 Propagation Delay from a Design Perspective
5.5 Power, Energy, and Energy Delay
5.5.1 Dynamic Power Consumption
5.5.2 Static Consumption
5.5.3 Putting It All Together
5.5.4 Analyzing Power Consumption Using SPICE
5.6 Perspective: Technology Scaling and its Impact on the Inverter Metrics
5.7 Summary
5.8 To Probe Further
References
Chapter 6 Designing Combinational Logic Gates in CMOS
6.1 Introduction
6.2 Static CMOS Design
6.2.1 Complementary CMOS
6.2.2 Ratioed Logic
6.2.3 Pass-Transistor Logic
6.3 Dynamic CMOS Design
6.3.1 Dynamic Logic: Basic Principles
6.3.2 Speed and Power Dissipation of Dynamic Logic
6.3.3 Signal Integrity Issues in Dynamic Design
6.3.4 Cascading Dynamic Gates
6.4 Perspectives
6.4.1 How to Choose a Logic Style?
6.4.2 Designing Logic for Reduced Supply Voltages
6.5 Summary
6.6 To Probe Further
References
Design Methodology Insert C How to Simulate Complex Logic Circuits
C.1 Representing Digital Data as a Continuous Entity
C.2 Representing Data as a Discrete Entity
C.3 Using Higher-Level Data Models
References
Design Methodology Insert D Layout Techniques for Complex Gates
Chapter 7 Designing Sequential Logic Circuits
7.1 Introduction
7.1.1 Timing Metrics for Sequential Circuits
7.1.2 Classification of Memory Elements
7.2 Static Latches and Registers
7.2.1 The Bistability Principle
7.2.2 Multiplexer-Based Latches
7.2.3 Master-Slave Edge-Triggered Register
7.2.4 Low-Voltage Static Latches
7.2.5 Static SR Flip-Flops Writing Data by Pure Force
7.3 Dynamic Latches and Registers
7.3.1 Dynamic Transmission-Gate Edge-triggered Registers
7.3.2 C2MOS--A Clock-Skew Insensitive Approach
7.3.3 True Single-Phase Clocked Register (TSPCR)
7.4 Alternative Register Styles*
7.4.1 Pulse Registers
7.4.2 Sense-Amplifier-Based Registers
7.5 Pipelining: An Approach to Optimize Sequential Circuits
7.5.1 Latch- versus Register-Based Pipelines
7.5.2 NORA-CMOS---A Logic Style for Pipelined Structures
7.6 Nonbistable Sequential Circuits
7.6.1 The Schmitt Trigger
7.6.2 Monostable Sequential Circuits
7.6.3 Astable Circuits
7.7 Perspective: Choosing a Clocking Strategy
7.8 Summary
7.9 To Probe Further
References
Part 3 A System Perspective
Chapter 8 Implementation Strategies for Digital ICS
8.1 Introduction
8.2 From Custom to Semicustom and Structured-Array Design Approaches
8.3 Custom Circuit Design
8.4 Cell-Based Design Methodology
8.4.1 Standard Cell
8.4.2 Compiled Cells
8.4.3 Macrocells, Megacells and Intellectual Property
8.4.4 Semicustom Design Flow
8.5 Array-Based Implementation Approaches
8.5.1 Prediffused (or Mask-Programmable) Arrays
8.5.2 Prewired Arrays
8.6 Perspective The Implementation Platform of the Future
8.7 Summary
8.8 To Probe Further
References
Design Methodology Insert E Characterizing Logic and Sequential Cells
References
Design Methodology Insert F Design Synthesis
References
Chapter 9 Coping with Interconnect
9.1 Introduction
9.2 Capacitive Parasitics
9.2.1 Capacitance and Reliability---Cross Talk
9.2.2 Capacitance and Performance in CMOS
9.3 Resistive Parasitics
9.3.1 Resistance and Reliability--Ohmic Voltage Drop
9.3.2 Electromigration
9.3.3 Resistance and Performance--RC Delay
9.4 Inductive Parasitics*
9.4.1 Inductance and Reliability-- Voltage Drop
9.4.2 Inductance and Performance Transmission-line Effects
9.5 Advanced Interconnect Techniques
9.5.1 Reduced-Swing Circuits
9.5.2 Current-Mode Transmission Techniques
9.6 Perspective: Networks-on-a-Chip
9.7 Summary
9.8 To Probe Further
References
Chapter 10 Timing Issues in Digital Circuits
10.1 Introduction
10.2 Timing Classification of Digital Systems
10.2.1 Synchronous Interconnect
10.2.2 Mesochronous interconnect
10.2.3 Plesiochronous Interconnect
10.2.4 Asynchronous Interconnect
10.3 Synchronous Design--An In-depth Perspective
10.3.1 Synchronous Timing Basics
10.3.2 Sources of Skew and Jitter
10.3.3 Clock-Distribution Techniques
10.3.4 Latch-Based Clocking
10.4 Self-Timed Circuit Design*
10.4.1 Self-Timed Logic--An Asynchronous Technique
10.4.2 Completion-Signal Generation
10.4.3 Self-Timed Signaling
10.4.4 Practical Examples of Self-Timed Logic
10.5 Synchronizers and Arbiters*
10.5.1 Synchronizers---Concept and Implementation
10.5.2 Arbiters
10.6 Clock Synthesis and Synchronization Using a Phase-Locked Loop*
10.6.1 Basic Concept
10.6.2 Building Blocks of a PLL
10.7 Future Directions and Perspectives
10.7.1 Distributed Clocking Using DLLs
10.7.2 Optical Clock Distribution
10.7.3 Synchronous versus Asynchronous Design
10.8 Summary
10.9 To Probe Further
References
Design Methodology Insert G Design Verification
References
Chapter 11 Designing Arithmetic Building Blocks
11.1 Introduction
11.2 Datapaths in Digital Processor Architectures
11.3 The Adder
11.3.1 The Binary Adder: Definitions
11.3.2 The Full Adder: Circuit Design Considerations
11.3.3 The Binary Adder: Logic Design Considerations
11.4 The Multiplier
11.4.1 The Multiplier: Definitions
11.4.2 Partial-Product Generation
11.4.3 Partial-Product Accumulation
11.4.4 Final Addition
11.4.5 Multiplier Summary
11.5 The Shifter
11.5.1 Barrel Shifter
11.5.2 Logarithmic Shifter
11.6 Other Arithmetic Operators
11.7 Power and Speed Trade-offs in Datapath Structures*
11.7.1 Design Time Power-Reduction Techniques
11.7.2 Run-Time Power Management
11.7.3 Reducing the Power in Standby (or Sleep) Mode
11.8 Perspective: Design as a Trade-off
11.9 Summary
11.10 To Probe Further
References
Chapter 12 Designing Memory and Array Structures
12.1 Introduction
12.1.1 Memory Classification
12.1.2 Memory Architectures and Building Blocks
12.2 The Memory Core
12.2.1 Read-Only Memories
12.2.2 Nonvolatile Read-Write Memories
12.2.3 Read-Write Memories (RAM)
12.2.4 Contents-Addressable or Associative Memory (CAM)
12.3 Memory Peripheral Circuitry*
12.3.1 The Address Decoders
12.3.2 Sense Amplifiers
12.3.3 Voltage References
12.3.4 Drivers/Buffers
12.3.5 Timing and Control
12.4 Memory Reliability and Yield*
12.4.1 Signal-to-Noise Ratio
12.4.2 Memory Yield
12.5 Power Dissipation in Memories*
12.5.1 Sources of Power Dissipation in Memories
12.5.2 Partitioning of the Memory
12.5.3 Addressing the Active Power Dissipation
12.5.4 Data-Retention Dissipation
12.5.5 Summary
12.6 Case Studies in Memory Design
12.6.1 The Programmable Logic Array (PLA)
12.6.2 A 4-Mbit SRAM
12.6.3 A 1-Gbit NAND Flash Memory
12.7 Perspective: Semiconductor Memory Trends and Evolutions
12.8 Summary
12.9 To Probe Further
References
Design Methodology Insert H Validation and Test of Manufactured Circuits
H. 1 Introduction
H.2 Test Procedure
H.3 Design for Testability
H.3.1 Issues in Design for Testability
H.3.2 Ad Hoc Testing
H.3.3 Scan-Based Test
H.3.4 Boundary-Scan Design
H.3.5 Built-in Self-Test (BIST)
H.4 Test-Pattern Generation
H.4.1 Fault Models
H.4.2 Automatic Test-Pattern Generation (ATPG)
H.4.3 Fault Simulation
H.5 To Probe Further
References
Problem Solutions
Indexs
Part 1 The Fabrics
Chapter 1 Introduction
1.1 A Historical Perspective
1.2 Issues in Digital Integrated Circuit Design
1.3 Quality Metrics of a Digital Design
1.3.1 Cost of an Integrated Circuit
1.3.2 Functionality and Robustness
1.3.3 Performance
1.3.4 Power and Energy Consumption
1.4 Summary
1.5 To Probe Further
Reference Books
References
Chapter 2 The Manufacturing Process
2.1 Introduction
2.2 Manufacturing CMOS Integrated Circuits
2.2.1 The Silicon Wafer
2.2.2 Photolithography
2.2.3 Some Recurring Process Steps
2.2.4 Simplified CMOS Process Flow
2.3 Design Rules-The Contract between Designer and Process Engineer
2.4 Packaging Integrated Circuits
2.4.1 Package Materials
2.4.2 Interconnect Levels
2.4.3 Thermal Considerations in Packaging
2.5 Perspective--Trends in Process Technology
2.5.1 Short-Term Developments
2.5.2 In the Longer Term
2.6 Summary
2.7 To Probe Further
References
Design Methodology Insert A IC LAYOUT
A.1 To Probe Further
References
Chapter 3 The Devices
3.1 Introduction
3.2 The Diode
3.2.1 A First Glance at the Diode--The Depletion Region
3.2.2 Static Behavior
3.2.3 Dynamic, or Transient, Behavior
3.2.4 The Actual Diode--Secondary Effects
3.2.5 The SPICE Diode Model
3.3 The MOS(FET) Transistor
3.3.1 A First Glance at the Device
3.3.2 The MOS Transistor under Static Conditions
3.3.3 The Actual MOS Transistor---Some Secondary Effects
3.3.4 SPICE Models for the MOS Transistor
3.4 A Word on Process Variations
3.5 Perspective--Technology Scaling
3.6 Summary
3.7 To Probe Further
References
Design Methodology Insert B Circuit Simulation
References
Chapter 4 The Wire
4.1 Introduction
4.2 A First Glance
4.3 Interconnect Parameters--Capacitance, Resistance, and Inductance
4.3.1 Capacitance
4.3.2 Resistance
4.3.3 Inductance
4.4 Electrical Wire Models
4.4.1 The Ideal Wire
4.4.2 The Lumped Model
4.4.3 The Lumped RC Model
4.4.4 The Distributed rc Line
4.4.5 The Transmission Line
SPICE Wire Models
4.5.1 Distributed rc Lines in SPICE
4.5.2 Transmission Line Models in SPICE
4.5.3 Perspective: A Look into the Future
4.6 Summary
4.7 To Probe Further
References
Part 2 A Circuit Perspective
Chapter 5 The CMOS Inverter
5.1 Introduction
5.2 The Static CMOS Inverter--An Intuitive Perspective
5.3 Evaluating the Robustness of the CMOS Inverter: The Static Behavior
5.3.1 Switching Threshold
5.3.2 Noise Margins
5.3.3 Robustness Revisited
5.4 Performance of CMOS Inverter: The Dynamic Behavior
5.4.1 Computing the Capacitances
5.4.2 Propagation Delay: First-Order Analysis
5.4.3 Propagation Delay from a Design Perspective
5.5 Power, Energy, and Energy Delay
5.5.1 Dynamic Power Consumption
5.5.2 Static Consumption
5.5.3 Putting It All Together
5.5.4 Analyzing Power Consumption Using SPICE
5.6 Perspective: Technology Scaling and its Impact on the Inverter Metrics
5.7 Summary
5.8 To Probe Further
References
Chapter 6 Designing Combinational Logic Gates in CMOS
6.1 Introduction
6.2 Static CMOS Design
6.2.1 Complementary CMOS
6.2.2 Ratioed Logic
6.2.3 Pass-Transistor Logic
6.3 Dynamic CMOS Design
6.3.1 Dynamic Logic: Basic Principles
6.3.2 Speed and Power Dissipation of Dynamic Logic
6.3.3 Signal Integrity Issues in Dynamic Design
6.3.4 Cascading Dynamic Gates
6.4 Perspectives
6.4.1 How to Choose a Logic Style?
6.4.2 Designing Logic for Reduced Supply Voltages
6.5 Summary
6.6 To Probe Further
References
Design Methodology Insert C How to Simulate Complex Logic Circuits
C.1 Representing Digital Data as a Continuous Entity
C.2 Representing Data as a Discrete Entity
C.3 Using Higher-Level Data Models
References
Design Methodology Insert D Layout Techniques for Complex Gates
Chapter 7 Designing Sequential Logic Circuits
7.1 Introduction
7.1.1 Timing Metrics for Sequential Circuits
7.1.2 Classification of Memory Elements
7.2 Static Latches and Registers
7.2.1 The Bistability Principle
7.2.2 Multiplexer-Based Latches
7.2.3 Master-Slave Edge-Triggered Register
7.2.4 Low-Voltage Static Latches
7.2.5 Static SR Flip-Flops Writing Data by Pure Force
7.3 Dynamic Latches and Registers
7.3.1 Dynamic Transmission-Gate Edge-triggered Registers
7.3.2 C2MOS--A Clock-Skew Insensitive Approach
7.3.3 True Single-Phase Clocked Register (TSPCR)
7.4 Alternative Register Styles*
7.4.1 Pulse Registers
7.4.2 Sense-Amplifier-Based Registers
7.5 Pipelining: An Approach to Optimize Sequential Circuits
7.5.1 Latch- versus Register-Based Pipelines
7.5.2 NORA-CMOS---A Logic Style for Pipelined Structures
7.6 Nonbistable Sequential Circuits
7.6.1 The Schmitt Trigger
7.6.2 Monostable Sequential Circuits
7.6.3 Astable Circuits
7.7 Perspective: Choosing a Clocking Strategy
7.8 Summary
7.9 To Probe Further
References
Part 3 A System Perspective
Chapter 8 Implementation Strategies for Digital ICS
8.1 Introduction
8.2 From Custom to Semicustom and Structured-Array Design Approaches
8.3 Custom Circuit Design
8.4 Cell-Based Design Methodology
8.4.1 Standard Cell
8.4.2 Compiled Cells
8.4.3 Macrocells, Megacells and Intellectual Property
8.4.4 Semicustom Design Flow
8.5 Array-Based Implementation Approaches
8.5.1 Prediffused (or Mask-Programmable) Arrays
8.5.2 Prewired Arrays
8.6 Perspective The Implementation Platform of the Future
8.7 Summary
8.8 To Probe Further
References
Design Methodology Insert E Characterizing Logic and Sequential Cells
References
Design Methodology Insert F Design Synthesis
References
Chapter 9 Coping with Interconnect
9.1 Introduction
9.2 Capacitive Parasitics
9.2.1 Capacitance and Reliability---Cross Talk
9.2.2 Capacitance and Performance in CMOS
9.3 Resistive Parasitics
9.3.1 Resistance and Reliability--Ohmic Voltage Drop
9.3.2 Electromigration
9.3.3 Resistance and Performance--RC Delay
9.4 Inductive Parasitics*
9.4.1 Inductance and Reliability-- Voltage Drop
9.4.2 Inductance and Performance Transmission-line Effects
9.5 Advanced Interconnect Techniques
9.5.1 Reduced-Swing Circuits
9.5.2 Current-Mode Transmission Techniques
9.6 Perspective: Networks-on-a-Chip
9.7 Summary
9.8 To Probe Further
References
Chapter 10 Timing Issues in Digital Circuits
10.1 Introduction
10.2 Timing Classification of Digital Systems
10.2.1 Synchronous Interconnect
10.2.2 Mesochronous interconnect
10.2.3 Plesiochronous Interconnect
10.2.4 Asynchronous Interconnect
10.3 Synchronous Design--An In-depth Perspective
10.3.1 Synchronous Timing Basics
10.3.2 Sources of Skew and Jitter
10.3.3 Clock-Distribution Techniques
10.3.4 Latch-Based Clocking
10.4 Self-Timed Circuit Design*
10.4.1 Self-Timed Logic--An Asynchronous Technique
10.4.2 Completion-Signal Generation
10.4.3 Self-Timed Signaling
10.4.4 Practical Examples of Self-Timed Logic
10.5 Synchronizers and Arbiters*
10.5.1 Synchronizers---Concept and Implementation
10.5.2 Arbiters
10.6 Clock Synthesis and Synchronization Using a Phase-Locked Loop*
10.6.1 Basic Concept
10.6.2 Building Blocks of a PLL
10.7 Future Directions and Perspectives
10.7.1 Distributed Clocking Using DLLs
10.7.2 Optical Clock Distribution
10.7.3 Synchronous versus Asynchronous Design
10.8 Summary
10.9 To Probe Further
References
Design Methodology Insert G Design Verification
References
Chapter 11 Designing Arithmetic Building Blocks
11.1 Introduction
11.2 Datapaths in Digital Processor Architectures
11.3 The Adder
11.3.1 The Binary Adder: Definitions
11.3.2 The Full Adder: Circuit Design Considerations
11.3.3 The Binary Adder: Logic Design Considerations
11.4 The Multiplier
11.4.1 The Multiplier: Definitions
11.4.2 Partial-Product Generation
11.4.3 Partial-Product Accumulation
11.4.4 Final Addition
11.4.5 Multiplier Summary
11.5 The Shifter
11.5.1 Barrel Shifter
11.5.2 Logarithmic Shifter
11.6 Other Arithmetic Operators
11.7 Power and Speed Trade-offs in Datapath Structures*
11.7.1 Design Time Power-Reduction Techniques
11.7.2 Run-Time Power Management
11.7.3 Reducing the Power in Standby (or Sleep) Mode
11.8 Perspective: Design as a Trade-off
11.9 Summary
11.10 To Probe Further
References
Chapter 12 Designing Memory and Array Structures
12.1 Introduction
12.1.1 Memory Classification
12.1.2 Memory Architectures and Building Blocks
12.2 The Memory Core
12.2.1 Read-Only Memories
12.2.2 Nonvolatile Read-Write Memories
12.2.3 Read-Write Memories (RAM)
12.2.4 Contents-Addressable or Associative Memory (CAM)
12.3 Memory Peripheral Circuitry*
12.3.1 The Address Decoders
12.3.2 Sense Amplifiers
12.3.3 Voltage References
12.3.4 Drivers/Buffers
12.3.5 Timing and Control
12.4 Memory Reliability and Yield*
12.4.1 Signal-to-Noise Ratio
12.4.2 Memory Yield
12.5 Power Dissipation in Memories*
12.5.1 Sources of Power Dissipation in Memories
12.5.2 Partitioning of the Memory
12.5.3 Addressing the Active Power Dissipation
12.5.4 Data-Retention Dissipation
12.5.5 Summary
12.6 Case Studies in Memory Design
12.6.1 The Programmable Logic Array (PLA)
12.6.2 A 4-Mbit SRAM
12.6.3 A 1-Gbit NAND Flash Memory
12.7 Perspective: Semiconductor Memory Trends and Evolutions
12.8 Summary
12.9 To Probe Further
References
Design Methodology Insert H Validation and Test of Manufactured Circuits
H. 1 Introduction
H.2 Test Procedure
H.3 Design for Testability
H.3.1 Issues in Design for Testability
H.3.2 Ad Hoc Testing
H.3.3 Scan-Based Test
H.3.4 Boundary-Scan Design
H.3.5 Built-in Self-Test (BIST)
H.4 Test-Pattern Generation
H.4.1 Fault Models
H.4.2 Automatic Test-Pattern Generation (ATPG)
H.4.3 Fault Simulation
H.5 To Probe Further
References
Problem Solutions
Indexs
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