书籍详情
数字系统测试和可测性设计（影印版）
作者： Miron Abramovici等著
出版社：清华大学出版社
出版时间：2004-01-01
ISBN：9787302077473
定价：¥65.00
购买这本书可以去
内容简介
Digital Systems Testing and Testable Design一书，是全美大学生和研究生优秀教材，比较系统地介绍了结构测试的理论和方法、可测性设计理论和度量方法、测试数据的处理及简化的理论和方法以及智能芯片（处理器、数字信号处理器和自动机等）测试理论和方法等。该书共有15章，分为3部分。前8章为第一部分，主要介绍数字系统、数字微系统芯片缺陷的来源、逻辑描述的方法——故障的建模、故障模拟、测试单固定故障、测试桥接故障、智能数字系统的功能测试及其范围等；第9章～第14章是第二部分，主要介绍数字系统的可测性设计理论和方法、建内自测试BIST测试数据压缩方法等现代测试理论和方法；第15章足第三部分，主要讨论系统测试的方法。该书概念清晰层次分明、定义和证明准确、算法推导和阐述简练。每章附有大量练习题可帮助读者对于概念的消化吸收。
作者简介
暂缺《数字系统测试和可测性设计（影印版）》作者简介
目录
PREFACE
HowThisBookWasWritten
1.INTRODUCTION
2.MODELING
2.1BasicConcepts
2.2FunctionalModelingattheLogicLevel
2.2.1TruthTablesandPrimitiveCubes
2.2.2StateTablesandFlowTables
2.2.3BinaryDecisionDiagrams
2.2.4ProgramsasFunctionalModels
2.3FunctionalModelingattheRegisterLevel
2.3.1BasicRTLConstructs
2.3.2TimingModelinginRTLs
2.3.3InternalRTLModels
2.4StructuralModels
2.4.1ExternalRepresentation
2.4.2StructuralProperties
2.4.3InternalRepresentation
2.4.4WiredLogicandBidirectionality
2.5LevelofModeling
REFERENCES
PROBLEMS
3.LOGICSIMULATiON
3.1Applications
3.2ProblemsinSimulation-BasedDesignVerification
3.3TypesofSimulation
3.4TheUnknownLogicValue
3.5CompiledSimulation
3.6Event-DrivenSimulation
3.7DelayModels
3.7.1DelayModelingforGates
3.7.2DelayModelingforFunctionalElements
3.7.3DelayModelinginRTLs
3.7.4OtherAspectsofDelayModeling
3.8ElementEvaluation
3.9HazardDetection
3.10Gate-LevelEvent-DrivenSimulation
3.10.1Transition-IndependentNominalTransportDelays
3.10.2OtherLogicValues
3.10.2.1TristateLogic
3.10.2.2MOSLogic
3.10.3OtherDelayModels
3.10.3.1RiseandFallDelays
3.10.3.2InertialDelays
3.10.3.3AmbiguousDelays
3.10.4OscillationControl
3.11SimulationEngines
REFERENCES
PROBLEMS
4.FAULTMODELING
4.1LogicalFaultModels
4.2FaultDetectionandRedundancy
4.2.1CombinationalCircuits
4.2.2SequentialCircuits
4.3FaultEquivalenceandFaultLocation
4.3.1CombinationalCircuits
4.3.2SequentialCircuits
4.4FaultDominance
4.4.1CombinationalCircuits
4.4.2SequentialCircuits
4.5TheSingleStuck-FaultModel
4.6TheMultipleStuck-FaultModel
4.7StuckRTLVariables
4.8FaultVariables
REFERENCES
PROBLEMS
5.FAULTSIMULATION
5.1Applications
5.2GeneralFaultSimulationTechniques
5.2.1SerialFaultSimulation
5.2.2CommonConceptsandTerminology
5.2.3ParallelFaultSimulation
5.2.4DeductiveFaultSimulation
5.2.4.1Two-ValuedDeductiveSimulation
5.2.4.2Three-ValuedDeductiveSimulation
5.2.5ConcurrentFaultSimulation
5.2.6Comparison
5.3FaultSimulationforCombinationalCircuits
5.3.1Parallel-PatternSingle-FaultPropagation
5.3.2CriticalPathTracing
5.4FaultSampling
5.5StatisticalFaultAnalysis
5.6ConcludingRemarks
REFERENCES
PROBLEMS
6.TESTINGFORSINGLESTUCKFAULTS
6.1BasicIssues
6.2ATGforSSFsinCombinationalCircuits
6.2.1Fault-OrientedATG
6.2.1.1CommonConcepts
6.2.1.2Algorithms
6.2.1.3SelectionCriteria
6.2.2Fault-IndependentATG
6.2.3RandomTestGeneration
6.2.3.1TheQualityofaRandomTest
6.2.3.2TheLengthofaRandomTest
6.2.3.3DeterminingDetectionProbabilities
6.2.3.4RTGwithNonuniformDistributions
6.2.4CombinedDeterministic/RandomTG
6.2.5ATGSystems
6.2.6OtherTGMethods
6.3ATGforSSFsinSequentialCircuits
6.3.1TGUsingIterativeArrayModels
6.3.2Simulation-BasedTG
6.3.3TGUsingRTLModels
6.3.3.1ExtensionsoftheD-Algorithm
6.3.3.2HeuristicState-SpaceSearch
6.3.4RandomTestGeneration
6.4ConcludingRemarks
REFERENCES
PROBLEMS
7.TESTINGFORBRIDGINGFAULTS
7.1TheBridging-FaultModel
7.2DetectionofNonfeedbackBridgingFaults
7.3DetectionofFeedbackBridgingFaults
7.4BridgingFaultsSimulation
7.5TestGenerationforBridgingFaults
7.6ConcludingRemarks
REFERENCES
PROBLEMS
8.FUNCTIONALTESTING
8.1BasicIssues
8.2FunctionalTestingWithoutFaultModels
8.2.1HeuristicMethods
8.2.2FunctionalTestingwithBinaryDecisionDiagrams
8.3ExhaustiveandPseudoexhaustiveTesting
8.3.1CombinationalCircuits
8.3.1.1Partial-DependenceCircuits
8.3.1.2PartitioningTechniques
8.3.2SequentialCircuits
8.3.3IterativeLogicArrays
8.4FunctionalTestingwithSpecificFaultModels
8.4.1FunctionalFaultModels
8.4.2FaultModelsforMicroprocessors
8.4.2.1FaultModelfortheRegister-DecodingFunction
8.4.2.2FaultModelfortheInstruction-DecodingandInstruction-SequencingFunction
8.4.2.3FaultModelfortheData-StorageFunction
8.4.2.4FaultModelfortheData-TransferFunction
8.4.2.5FaultModelfortheData-ManipulationFunction
8.4.3TestGenerationProcedures
8.4.3.1TestingtheRegister-DecodingFunction
8.4.3.2TestingtheInstruction-DecodingandInstruction-SequencingFunction
8.4.3.3TestingtheData-StorageandData-TransferFunctions
8.4.4ACaseStudy
8.5ConcludingRemarks
REFERENCES
PROBLEMS
9.DESIGNFORTESTABILITY
9.1Testability
9.1.1Trade-Offs
9.1.2ControllabilityandObservability
9.2AdHocDesignforTestabilityTechniques
9.2.1TestPoints
9.2.2Initialization
9.2.3MonostableMultivibrators
9.2.4OscillatorsandClocks
9.2.5PartitioningCountersandShiftRegisters
9.2.6PartitioningofLargeCombinationalCircuits
9.2.7LogicalRedundancy
9.2.8GlobalFeedbackPaths
9.3ControllabilityandObservabilitybyMeansofScanRegisters
9.3.1GenericBoundaryScan
9.4GenericScan-BasedDesigns
9.4.1FullSerialIntegratedScan
9.4.2IsolatedSerialScan
9.4.3NonserialScan
9.5StorageCellsforScanDesigns
9.6ClassicalScanDesigns
9.7ScanDesignCosts
9.8Board-LevelandSystem-LevelDFTApproaches
9.8.1System-LevelBusses
9.8.2System-LevelScanPaths
9.9SomeAdvancedScanConcepts
9.9.1MultipleTestSession
9.9.2PartialScanUsingI-Paths
9.9.3BALLAST--AStructuredPartialScanDesign
9.10BoundaryScanStandards
9.10.1Background
9.10.2BoundaryScanCell
9.10.3BoardandChipTestModes
9.10.4TheTestBus
9.10.5TestBusCircuitry
9.10.5.1TheTAPController
9.10.5.2Registers
REFERENCES
PROBLEMS
10.COMPRESSIONTECHNIQUES
10.1GeneralAspectsofCompressionTechniques
10.2Ones-CountCompression
10.3Transition-CountCompression
10.4Parity-CheckCompression
10.5SyndromeTesting
10.6SignatureAnalysis
10.6.1TheoryandOperationofLinearFeedbackShiftRegisters
10.6.2LFSRsUsedasSignatureAnalyzers
10.6.3Multiple-InputSignatureRegisters
10.7ConcludingRemarks
REFERENCES
PROBLEMS
11.BUILT-INSELF-TEST
11.1IntroductiontoBISTConcepts
11.1.1Hardcore
11.1.2LevelsofTest
11.2Test-PatternGenerationforBIST
11.2.1ExhaustiveTesting
11.2.2PseudorandomTesting
11.2.3PseudoexhaustiveTesting
11.2.3.1LogicalSegmentation
11.2.3.2Constant-WeightPatterns
11.2.3.3IdentificationofTestSignalInputs
11.2.3.4TestPatternGeneratorsforPseudoexhaustiveTests
11.2.3.5PhysicalSegmentation
11.3GenericOff-LineBISTArchitectures
11.4SpecificBISTArchitectures
11.4.1ACentralizedandSeparateBoard-LevelBISTArchitecture(CSBL)
11.4.2Built-InEvaluationandSelf-Test(BEST)
11.4.3Random-TestSocket(RTS)
11.4.4LSSDOn-ChipSelf-Test(LOCST)
11.4.5Self-TestingUsingMISRandParallelSRSG(STUMPS)
11.4.6AConcurrentBISTArchitecture(CBIST)
11.4.7ACentralizedandEmbeddedBISTArchitecturewithBoundaryScan(CEBS)
11.4.8RandomTestData(RTD)
11.4.9SimultaneousSelf-Test(SST)
11.4.10CyclicAnalysisTestingSystem(CATS)
11.4.11CircularSelf-TestPath(CSTP)
11.4.12Built-InLogic-BlockObservation(BILBO)
11.4.12.1CaseStudy
11.4.13Summary
11.5SomeAdvancedBISTConcepts
11.5.1TestSchedules
11.5.2ControlofBILBORegisters
11.5.3Partial-IntrusionBIST
11.6DesignforSelf-TestatBoardLevel
REFERENCES
PROBLEMS
12.LOGIC-LEVELDIAGNOSIS
12.1BasicConcepts
12.2FaultDictionary
12.3Guided-ProbeTesting
12.4DiagnosisbyUUTReduction
12.5FaultDiagnosisforCombinationalCircuits
12.6ExpertSystemsforDiagnosis
12.7Effect-CauseAnalysis
12.8DiagnosticReasoningBasedonStructureandBehavior
REFERENCES
PROBLEMS
13.SELF-CHECKINGDESIGN
13.1BasicConcepts
13.2ApplicationofError-DetectingandError-CorrectingCodes
13.3Multiple-BitErrors
13.4CheckingCircuitsandSelf-Checking
13.5Self-CheckingCheckers
13.6Parity-CheckFunction
13.7TotallySelf-Checkingm/nCodeCheckers
13.8TotallySelf-CheckingEqualityCheckers
13.9Self-CheckingBergerCodeCheckers
13.10TowardaGeneralTheoryofSelf-CheckingCombinationalCircuits
13.11Self-CheckingSequentialCircuits
REFERENCES
PROBLEMS
14.PLATESTING
14.1Introduction
14.2PLATestingProblems
14.2.1FaultModels
14.2.2ProblemswithTraditionalTestGenerationMethods
14.3TestGenerationAlgorithmsforPLAs
14.3.1DeterministicTestGeneration
14.3.2SemirandomTestGeneration
14.4TestablePLADesigns
14.4.1ConcurrentTestablePLAswithSpecialCoding
14.4.1.1PLAwithConcurrentErrorDetectionbyaSeriesofCheckers
14.4.1.2ConcurrentTestablePLAsUsingModifiedBergerCode
14.4.2ParityTestablePLAs
14.4.2.1PLAwithUniversalTestSet
14.4.2.2AutonomouslyTestablePLAs
14.4.2.3ABuilt-InSelf-TestablePLADesignwithCumulativeParityComparison
14.4.3Signature-TestablePLAs
14.4.3.1PLAwithMultipleSignatureAnalyzers
14.4.3.2Self-TestablePLAswithSingleSignatureAnalyzer
14.4.4PartioningandTestingofPLAs
14.4.4.1PLAwithBILBOs
14.4.4.2Parallel-TestablePLAs
14.4.4.3Divide-and-ConquerStrategyforTestablePLADesign
14.4.5Fully-TestablePLADesigns
14.5EvaluationofPLATestMethodologies
14.5.1MeasuresofTDMs
14.5.1.1ResultingEffectontheOriginalDesign
14.5.1.2RequirementsonTestEnvironment
14.5.2EvaluationofPLATestTechniques
REFERENCES
PROBLEMS
15.SYSTEM-LEVELDIAGNOSIS
15.1ASimpleModelofSystem-LevelDiagnosis
15.2GeneralizationsofthePMCModel
15.2.1GeneralizationsoftheSystemDiagnosticGraph
15.2.2GeneralizationofPossibleTestOutcomes
15.2.3GeneralizationofDiagnosabilityMeasures
REFERENCES
PROBLEMS
INDEX
HowThisBookWasWritten
1.INTRODUCTION
2.MODELING
2.1BasicConcepts
2.2FunctionalModelingattheLogicLevel
2.2.1TruthTablesandPrimitiveCubes
2.2.2StateTablesandFlowTables
2.2.3BinaryDecisionDiagrams
2.2.4ProgramsasFunctionalModels
2.3FunctionalModelingattheRegisterLevel
2.3.1BasicRTLConstructs
2.3.2TimingModelinginRTLs
2.3.3InternalRTLModels
2.4StructuralModels
2.4.1ExternalRepresentation
2.4.2StructuralProperties
2.4.3InternalRepresentation
2.4.4WiredLogicandBidirectionality
2.5LevelofModeling
REFERENCES
PROBLEMS
3.LOGICSIMULATiON
3.1Applications
3.2ProblemsinSimulation-BasedDesignVerification
3.3TypesofSimulation
3.4TheUnknownLogicValue
3.5CompiledSimulation
3.6Event-DrivenSimulation
3.7DelayModels
3.7.1DelayModelingforGates
3.7.2DelayModelingforFunctionalElements
3.7.3DelayModelinginRTLs
3.7.4OtherAspectsofDelayModeling
3.8ElementEvaluation
3.9HazardDetection
3.10Gate-LevelEvent-DrivenSimulation
3.10.1Transition-IndependentNominalTransportDelays
3.10.2OtherLogicValues
3.10.2.1TristateLogic
3.10.2.2MOSLogic
3.10.3OtherDelayModels
3.10.3.1RiseandFallDelays
3.10.3.2InertialDelays
3.10.3.3AmbiguousDelays
3.10.4OscillationControl
3.11SimulationEngines
REFERENCES
PROBLEMS
4.FAULTMODELING
4.1LogicalFaultModels
4.2FaultDetectionandRedundancy
4.2.1CombinationalCircuits
4.2.2SequentialCircuits
4.3FaultEquivalenceandFaultLocation
4.3.1CombinationalCircuits
4.3.2SequentialCircuits
4.4FaultDominance
4.4.1CombinationalCircuits
4.4.2SequentialCircuits
4.5TheSingleStuck-FaultModel
4.6TheMultipleStuck-FaultModel
4.7StuckRTLVariables
4.8FaultVariables
REFERENCES
PROBLEMS
5.FAULTSIMULATION
5.1Applications
5.2GeneralFaultSimulationTechniques
5.2.1SerialFaultSimulation
5.2.2CommonConceptsandTerminology
5.2.3ParallelFaultSimulation
5.2.4DeductiveFaultSimulation
5.2.4.1Two-ValuedDeductiveSimulation
5.2.4.2Three-ValuedDeductiveSimulation
5.2.5ConcurrentFaultSimulation
5.2.6Comparison
5.3FaultSimulationforCombinationalCircuits
5.3.1Parallel-PatternSingle-FaultPropagation
5.3.2CriticalPathTracing
5.4FaultSampling
5.5StatisticalFaultAnalysis
5.6ConcludingRemarks
REFERENCES
PROBLEMS
6.TESTINGFORSINGLESTUCKFAULTS
6.1BasicIssues
6.2ATGforSSFsinCombinationalCircuits
6.2.1Fault-OrientedATG
6.2.1.1CommonConcepts
6.2.1.2Algorithms
6.2.1.3SelectionCriteria
6.2.2Fault-IndependentATG
6.2.3RandomTestGeneration
6.2.3.1TheQualityofaRandomTest
6.2.3.2TheLengthofaRandomTest
6.2.3.3DeterminingDetectionProbabilities
6.2.3.4RTGwithNonuniformDistributions
6.2.4CombinedDeterministic/RandomTG
6.2.5ATGSystems
6.2.6OtherTGMethods
6.3ATGforSSFsinSequentialCircuits
6.3.1TGUsingIterativeArrayModels
6.3.2Simulation-BasedTG
6.3.3TGUsingRTLModels
6.3.3.1ExtensionsoftheD-Algorithm
6.3.3.2HeuristicState-SpaceSearch
6.3.4RandomTestGeneration
6.4ConcludingRemarks
REFERENCES
PROBLEMS
7.TESTINGFORBRIDGINGFAULTS
7.1TheBridging-FaultModel
7.2DetectionofNonfeedbackBridgingFaults
7.3DetectionofFeedbackBridgingFaults
7.4BridgingFaultsSimulation
7.5TestGenerationforBridgingFaults
7.6ConcludingRemarks
REFERENCES
PROBLEMS
8.FUNCTIONALTESTING
8.1BasicIssues
8.2FunctionalTestingWithoutFaultModels
8.2.1HeuristicMethods
8.2.2FunctionalTestingwithBinaryDecisionDiagrams
8.3ExhaustiveandPseudoexhaustiveTesting
8.3.1CombinationalCircuits
8.3.1.1Partial-DependenceCircuits
8.3.1.2PartitioningTechniques
8.3.2SequentialCircuits
8.3.3IterativeLogicArrays
8.4FunctionalTestingwithSpecificFaultModels
8.4.1FunctionalFaultModels
8.4.2FaultModelsforMicroprocessors
8.4.2.1FaultModelfortheRegister-DecodingFunction
8.4.2.2FaultModelfortheInstruction-DecodingandInstruction-SequencingFunction
8.4.2.3FaultModelfortheData-StorageFunction
8.4.2.4FaultModelfortheData-TransferFunction
8.4.2.5FaultModelfortheData-ManipulationFunction
8.4.3TestGenerationProcedures
8.4.3.1TestingtheRegister-DecodingFunction
8.4.3.2TestingtheInstruction-DecodingandInstruction-SequencingFunction
8.4.3.3TestingtheData-StorageandData-TransferFunctions
8.4.4ACaseStudy
8.5ConcludingRemarks
REFERENCES
PROBLEMS
9.DESIGNFORTESTABILITY
9.1Testability
9.1.1Trade-Offs
9.1.2ControllabilityandObservability
9.2AdHocDesignforTestabilityTechniques
9.2.1TestPoints
9.2.2Initialization
9.2.3MonostableMultivibrators
9.2.4OscillatorsandClocks
9.2.5PartitioningCountersandShiftRegisters
9.2.6PartitioningofLargeCombinationalCircuits
9.2.7LogicalRedundancy
9.2.8GlobalFeedbackPaths
9.3ControllabilityandObservabilitybyMeansofScanRegisters
9.3.1GenericBoundaryScan
9.4GenericScan-BasedDesigns
9.4.1FullSerialIntegratedScan
9.4.2IsolatedSerialScan
9.4.3NonserialScan
9.5StorageCellsforScanDesigns
9.6ClassicalScanDesigns
9.7ScanDesignCosts
9.8Board-LevelandSystem-LevelDFTApproaches
9.8.1System-LevelBusses
9.8.2System-LevelScanPaths
9.9SomeAdvancedScanConcepts
9.9.1MultipleTestSession
9.9.2PartialScanUsingI-Paths
9.9.3BALLAST--AStructuredPartialScanDesign
9.10BoundaryScanStandards
9.10.1Background
9.10.2BoundaryScanCell
9.10.3BoardandChipTestModes
9.10.4TheTestBus
9.10.5TestBusCircuitry
9.10.5.1TheTAPController
9.10.5.2Registers
REFERENCES
PROBLEMS
10.COMPRESSIONTECHNIQUES
10.1GeneralAspectsofCompressionTechniques
10.2Ones-CountCompression
10.3Transition-CountCompression
10.4Parity-CheckCompression
10.5SyndromeTesting
10.6SignatureAnalysis
10.6.1TheoryandOperationofLinearFeedbackShiftRegisters
10.6.2LFSRsUsedasSignatureAnalyzers
10.6.3Multiple-InputSignatureRegisters
10.7ConcludingRemarks
REFERENCES
PROBLEMS
11.BUILT-INSELF-TEST
11.1IntroductiontoBISTConcepts
11.1.1Hardcore
11.1.2LevelsofTest
11.2Test-PatternGenerationforBIST
11.2.1ExhaustiveTesting
11.2.2PseudorandomTesting
11.2.3PseudoexhaustiveTesting
11.2.3.1LogicalSegmentation
11.2.3.2Constant-WeightPatterns
11.2.3.3IdentificationofTestSignalInputs
11.2.3.4TestPatternGeneratorsforPseudoexhaustiveTests
11.2.3.5PhysicalSegmentation
11.3GenericOff-LineBISTArchitectures
11.4SpecificBISTArchitectures
11.4.1ACentralizedandSeparateBoard-LevelBISTArchitecture(CSBL)
11.4.2Built-InEvaluationandSelf-Test(BEST)
11.4.3Random-TestSocket(RTS)
11.4.4LSSDOn-ChipSelf-Test(LOCST)
11.4.5Self-TestingUsingMISRandParallelSRSG(STUMPS)
11.4.6AConcurrentBISTArchitecture(CBIST)
11.4.7ACentralizedandEmbeddedBISTArchitecturewithBoundaryScan(CEBS)
11.4.8RandomTestData(RTD)
11.4.9SimultaneousSelf-Test(SST)
11.4.10CyclicAnalysisTestingSystem(CATS)
11.4.11CircularSelf-TestPath(CSTP)
11.4.12Built-InLogic-BlockObservation(BILBO)
11.4.12.1CaseStudy
11.4.13Summary
11.5SomeAdvancedBISTConcepts
11.5.1TestSchedules
11.5.2ControlofBILBORegisters
11.5.3Partial-IntrusionBIST
11.6DesignforSelf-TestatBoardLevel
REFERENCES
PROBLEMS
12.LOGIC-LEVELDIAGNOSIS
12.1BasicConcepts
12.2FaultDictionary
12.3Guided-ProbeTesting
12.4DiagnosisbyUUTReduction
12.5FaultDiagnosisforCombinationalCircuits
12.6ExpertSystemsforDiagnosis
12.7Effect-CauseAnalysis
12.8DiagnosticReasoningBasedonStructureandBehavior
REFERENCES
PROBLEMS
13.SELF-CHECKINGDESIGN
13.1BasicConcepts
13.2ApplicationofError-DetectingandError-CorrectingCodes
13.3Multiple-BitErrors
13.4CheckingCircuitsandSelf-Checking
13.5Self-CheckingCheckers
13.6Parity-CheckFunction
13.7TotallySelf-Checkingm/nCodeCheckers
13.8TotallySelf-CheckingEqualityCheckers
13.9Self-CheckingBergerCodeCheckers
13.10TowardaGeneralTheoryofSelf-CheckingCombinationalCircuits
13.11Self-CheckingSequentialCircuits
REFERENCES
PROBLEMS
14.PLATESTING
14.1Introduction
14.2PLATestingProblems
14.2.1FaultModels
14.2.2ProblemswithTraditionalTestGenerationMethods
14.3TestGenerationAlgorithmsforPLAs
14.3.1DeterministicTestGeneration
14.3.2SemirandomTestGeneration
14.4TestablePLADesigns
14.4.1ConcurrentTestablePLAswithSpecialCoding
14.4.1.1PLAwithConcurrentErrorDetectionbyaSeriesofCheckers
14.4.1.2ConcurrentTestablePLAsUsingModifiedBergerCode
14.4.2ParityTestablePLAs
14.4.2.1PLAwithUniversalTestSet
14.4.2.2AutonomouslyTestablePLAs
14.4.2.3ABuilt-InSelf-TestablePLADesignwithCumulativeParityComparison
14.4.3Signature-TestablePLAs
14.4.3.1PLAwithMultipleSignatureAnalyzers
14.4.3.2Self-TestablePLAswithSingleSignatureAnalyzer
14.4.4PartioningandTestingofPLAs
14.4.4.1PLAwithBILBOs
14.4.4.2Parallel-TestablePLAs
14.4.4.3Divide-and-ConquerStrategyforTestablePLADesign
14.4.5Fully-TestablePLADesigns
14.5EvaluationofPLATestMethodologies
14.5.1MeasuresofTDMs
14.5.1.1ResultingEffectontheOriginalDesign
14.5.1.2RequirementsonTestEnvironment
14.5.2EvaluationofPLATestTechniques
REFERENCES
PROBLEMS
15.SYSTEM-LEVELDIAGNOSIS
15.1ASimpleModelofSystem-LevelDiagnosis
15.2GeneralizationsofthePMCModel
15.2.1GeneralizationsoftheSystemDiagnosticGraph
15.2.2GeneralizationofPossibleTestOutcomes
15.2.3GeneralizationofDiagnosabilityMeasures
REFERENCES
PROBLEMS
INDEX
猜您喜欢
