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逻辑设计基础：英文版
作者：（美）Charles H.Roth，Jr.著
出版社：机械工业出版社
出版时间：2003-10-01
ISBN：9787111123514
定价：¥68.00
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内容简介
本书详细地阐述了理解逻辑设计基本概念所必需的理论，同时又不过多地讨论开关理论的数学证明。全书共分20个单元，包括布尔代数。逻辑门设计、触发器、状态机等基本概念。通过将触发器和逻辑门网络相结合，学生将学会如何设计计数器、加法器、序列检测器和简单的数字系统。在介绍完这些基础概念之后，本书使用可编程逻辑设备和VHDL硬件描述语言介绍了现代的设计技术。本书全面介绍了数字系统逻辑设计的基本概念，在理论和实践之间做到了很好的平衡。可用做电子工程和计算机系学生学习数字系统逻辑设计的入门教材，并为学生进一步学习数字系统设计和开关理论的高级知识奠定了基础，同时本书也是理想的自学教材。特点：●开关电路的基本理论及其应用。●每章的开始都有学习指南，包括指定阅读部分和需要学习的问题。每章最开始出现的学习目标精确地指出学生将会从本学习单元学到什么知识。●包括模拟或实验室的练习，为学生提供机会去设计逻辑电路并随后在运行中进行测试。●随书附带的光盘中有三个对于计算机辅助设计和数字逻辑模拟非常有用的程序：LogicAid、SimUaid和DirectVHDL-PE。作者简介：CharlesH．Roth，Jr．分别在明尼苏达大学、麻省理工学院和斯坦福大学的电子工程系获得学士、硕士和博士学位，并于1961年加入得克萨斯大学奥斯汀分校任教，目前他是该校电子和计算机工程系的教授。他在逻辑设计的教学中开发了一种自定学习进度的教程，因其杰出的工程教学效果而获得GeneralDynamics奖。他的教学和研究领域包括：数字系统理论和设计、微计算机系统、VHDL应用等。
作者简介
CharlesH.Roth，Jr.分别是明尼苏达大学、麻省理工学院和斯坦福大学的电子工程系获得学士、硕士和学位，并于1961年加入得克萨斯大学奥斯汀分校任教，目前他是该校电子和计算机工程系的教授。他在逻辑设计的教学中开发了一种自定学习进度的教程，因其杰出的工程教学效果而获得GeneralDynamics奖。他的教学和研究领域包括：数字系统理论和设计、微计算机系统、VHDL应用等。
目录
Brief Contents
1 Introduction
Number Systems and Conversion
2 Boolean Algebra
3 Boolean Algebra(Continued)
4 Applications of Boolean Algebra
Minterm and Maxterm Expansions
5 Karnaugh Maps
6 Quine-McCluskey Methce
7 Multi-Level Gate Circuits
NAND and NOR Gates
8 Combinational Circuit Design and Simulation Using Gates
9 Multiplexers,Declders,and Programmable
Logic Devices
10 Introduction to VHDL
11 Latches and Flip-Flops
12 Registers and Counters
13 Analysis of Clocded Sequential Circuits
14 Derivation of State Graphs and Tables
15 Reduction of State Table
State Assignment
16 Sequential Circuit Design
17 VHDL for Sequential Logic
18 Circrits for Arithmetic Operations
19 State Machine Desingn with SM Charts
20 VHDL for Digital System Design
A Appendices
Contents
Preface
How to Use This Book for Self-Study
1 Introduxtion
Number Systems and Conversion
Objectives
Study Guide
1.1 Digital Systems and Switching Circuits
1.2 Number Systems and Conversion
1.3 Binary Arithmetic
1.4 Representation of Negative Numbers
Addition of 2's Complement Numbers
Addition fo 1's Complement Numbers
1.5 Binary Codes
Problems
2 Boolean Algebra
Objectives
Study Guide
2.1 Introduction
2.2 Basic Operations
2.3 Boolean Expressions and Truth Tables
2.4 Basic Theorems
2.5 Commutative,Associative,and Distributive Laws
2.6 Simplification Theouems
2.7 Multiplying Out and Factouing
2.8 DeMorgan's Laws
Problems
Laws and Theorems of Boolean Algebra
3 Boolean Algebra (Continued)
Objective
Study Guide
3.1 Multiplying Out and Factoring Expressions
3.2 Exclusive-OR and Factoring Expressions
3.3 The Consensus Theorem
3.4 Algebraic Simplification of Switching Wxpressions
3.5 Proving the Validity of an Equation
Programmed Exercises
Problems
4 Applications of Boolean Algebra
Minterm and Maxterm Expansions
Objectives
Study Guide
4.1 Conversion of English Sentencse to Boolean Equations
4.2 Combinational Logic Design Using a Truth Table
4.3 Mimterm and Maxterm Expansions
4.4 General Minterm and Maxterm Expansions
4.5 Incompletely Specified Functions
4.6 Examples of Truth Table Construction
4.7 Design of Binary Adders and Subtracters
Problems
5 Karnaugh Maps
Objectives
Study Guide
5.1 Minimum Forms of Switching Functions
5.2 Two-and Three-Variable Karnaugh Maps
5.3 Four-Variable Karanugh Maps
5.4 Determination of Minimum Expressions
Using Essential Prime Implicants
5.5 Five-Varable Karnaugh Maps
5.6 Other Used of Karnaugh Maps
5.7 Other Forms of Karnaugh Maps
Programmed Exercises
Problems
6 Quine-McCluskey Method
Objectives
Study Guide
6.1 Determination of Prime Implicants
6.2 The Prime Implicant Chart
6.3 Petrick's Method
6.4 Simplification of Incompletely Specified Functions
6.5 Simplification Using Map-Entered Variableds
6.6 Conclusion
Programmde Exercise
Problems
7 Multi-Level Gate CirCuits
NAND and NOR Gates
Objectives
Study Guide
7.1 Multi-Level Gate Circuits
7.2 NAND and NOR Gates
7.3 Design of Two-Level Circrits Using NAND and NOR Gates
7.4 Design of Multi-Level NAND and NOR Gate Circuits
7.5 Circuit Conversion Using Alternative Gate Symbols
7.6 Delign of Two-Level,Multiple-Ortput Circuits
Determination of Essential Prime Implicants for
Multiple-Output Realization
7.7 Multiple-Output NAND and NRO Circuits
8 Combinational Circuit Design
and Simulation Using Gates
Objectives
Study Guide
8.1 Review of Combinational Circuit Design
8.2 Design of Corcuits with Limited Gate Fan-In
8.3 Gate Delays and Timing Diagrams
8.4 Hazards in Combinational Logic
8.5 Simultion and Testion of Logic Circuits
Problems
Design Problems
9 Multiplexers,Declders,and Programmable
Logic Devices
Objectives
Study Guide
9.1 Introduction
9.2 Multiplexers
9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices
Programmable Logic Arrays
Programmable Array Logic
9.7 Complex Programmable Logic Devices
9.8 Field Programmable Gate Arrays
Decomposition of Switching Fumctions
Problems
10 Introduction to VHDL
Objetives
Study Guide
10.1 VHDL Description of Combinational Circuits
10.2 VHDL Models for Multplexers
10.3 VHDL Modules
Four-Bit Full Adder
10.4 Signals and Constants
10.5 Arrays
10.6 VHDL Operators
10.7 Packages and Libraries
10.8 IEEE Stanedard Logic
10.9 Compilation and Simulation of VHDL Code
Problems
11 Latches and Flip-Flops
Objectives
Study Guide
11.1 Introduction
11.2 Set-Reset Latch
11.3 Gated D Latch
11.4 Edge-Triggerde D Flip-Flop
11.5 S-R FLIP-Flop
11.6 J-K Flip-Flop
11.7 T Flip-Flop
11.8 Flip-Flops with Additional Inputs
11.9 Summary
Prlblems
Programmde Exercise
12 Registers and Counters
Objectives
Study Guide
12.1 Registers and Register Transfers
Parallel Adder with Accumulator
12.2 Shift Registers
12.3 Design of Binary Counters
12.4 Counters for Other Sequences
Counters Design Using D Flip-Flops
12.5 Counter Design Using S-R and J-K Filp-Flops
12.6 Derivation of Flip-Flop Input Equations-Summary
Problems
13 Analysis of Clocked Sequential Circuits
Objectives
Study Guide
13.1 A Sequential Parety Checker
13.2 Analysis by Signal Tracing and Timing Charts
13.3 State Tables and Graphs
Construction and Interpretation of Timing Charts
13.4 General Models for Sequential Circuits
Programmed Exercise
Problems
14 Derivation of State Graphs and Tables
Objebtives
Study Guide
14.1 Design of a Sequence Detector
14.2 More Complex Design Problems
14.3 Guidelines rlf Comstruction of State Graphs
14.4 Serial Data Code Conversion
14.5 Alphanumeric State Graph Notation
Programmed Exercises
Probleml
15 Reduction of State Tables
State Assignment
Objectives
Study Guide
15.1 Elimination of Redundant States
15.2 Equivalent States
15.3 Determination of State Equivalence Using an Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incmpletely Specified State Tables
15.6 Derivation of Flip-Folp Input Equations
15.7 Equivalent State Assignments
15.8 Guidelines for State Assignment
15.9 Using a One-Hot State Assignment
Problems
16 Sequential Circuit Design
Objectives
Study Guide
16.1 Summary of Design Procedure for Sequential Circuits
16.2 Design Example-Code Converter
16.3 Design of Iterative Circuits
Design of a Comparator
16.4 Design of Sequential Circuits Using ROMs and PLAs
16.5 Sequential Circuit Design Using CPLDs
16.6 Sequential Circuit Design Using FPGAs
16.7 Simulation and Testing of Sequrential Circuits
16.8 Overview of Computer-Aided Design
Design Problems
Additional Problems
17 VHDL for Sequential Logic
Objectives
Study Guide
17.1 Modeling Flip-Flops Using VHDL Processes
17.2 Modeling Registers and Counters Using VHDL Processes
17.3 Modeling Combinational Logic Using VHDL Processes
17.4 Modeling a Sequential Machine
17.5 Synthesis of VHDL Code
17.6 More about Processes and Sequential Statements
Problems
Simulation Prlblems
18 Circuits for Arithmetic Operations
Objectives
Study Guide
18.1 Serial Adder with Accumulator
18.2 Design of a Parallel Multiplier
18.3 Design of a Binary Divider
Programmed Exercises
Prlblems
19 State Machine Design with SM Charts
Objectives
Study Guide
19.1 State Machine Charts
19.2 Derivation of SM Charts
19.3 Realization of SM Charts
Problems
20 VHDL for Digital System Design
Objectives
Study Guide
20.1 VHDL Code for a Serial Adder
20.2 VHDL Code for a Binary Multiplier
20.3 VHDL Code for a Binary Divider
20.4 VHDL Code for a Dice Game Simulator
20.5 Concluding Remarks
Problems
Lab Design Problems
A Appendices
A MOS and COMS Logic
B VHDL Language Summary
C Proofs of Theorems
References
Answers to Selected Study Guide
Questions and Problems
Index
1 Introduction
Number Systems and Conversion
2 Boolean Algebra
3 Boolean Algebra(Continued)
4 Applications of Boolean Algebra
Minterm and Maxterm Expansions
5 Karnaugh Maps
6 Quine-McCluskey Methce
7 Multi-Level Gate Circuits
NAND and NOR Gates
8 Combinational Circuit Design and Simulation Using Gates
9 Multiplexers,Declders,and Programmable
Logic Devices
10 Introduction to VHDL
11 Latches and Flip-Flops
12 Registers and Counters
13 Analysis of Clocded Sequential Circuits
14 Derivation of State Graphs and Tables
15 Reduction of State Table
State Assignment
16 Sequential Circuit Design
17 VHDL for Sequential Logic
18 Circrits for Arithmetic Operations
19 State Machine Desingn with SM Charts
20 VHDL for Digital System Design
A Appendices
Contents
Preface
How to Use This Book for Self-Study
1 Introduxtion
Number Systems and Conversion
Objectives
Study Guide
1.1 Digital Systems and Switching Circuits
1.2 Number Systems and Conversion
1.3 Binary Arithmetic
1.4 Representation of Negative Numbers
Addition of 2's Complement Numbers
Addition fo 1's Complement Numbers
1.5 Binary Codes
Problems
2 Boolean Algebra
Objectives
Study Guide
2.1 Introduction
2.2 Basic Operations
2.3 Boolean Expressions and Truth Tables
2.4 Basic Theorems
2.5 Commutative,Associative,and Distributive Laws
2.6 Simplification Theouems
2.7 Multiplying Out and Factouing
2.8 DeMorgan's Laws
Problems
Laws and Theorems of Boolean Algebra
3 Boolean Algebra (Continued)
Objective
Study Guide
3.1 Multiplying Out and Factoring Expressions
3.2 Exclusive-OR and Factoring Expressions
3.3 The Consensus Theorem
3.4 Algebraic Simplification of Switching Wxpressions
3.5 Proving the Validity of an Equation
Programmed Exercises
Problems
4 Applications of Boolean Algebra
Minterm and Maxterm Expansions
Objectives
Study Guide
4.1 Conversion of English Sentencse to Boolean Equations
4.2 Combinational Logic Design Using a Truth Table
4.3 Mimterm and Maxterm Expansions
4.4 General Minterm and Maxterm Expansions
4.5 Incompletely Specified Functions
4.6 Examples of Truth Table Construction
4.7 Design of Binary Adders and Subtracters
Problems
5 Karnaugh Maps
Objectives
Study Guide
5.1 Minimum Forms of Switching Functions
5.2 Two-and Three-Variable Karnaugh Maps
5.3 Four-Variable Karanugh Maps
5.4 Determination of Minimum Expressions
Using Essential Prime Implicants
5.5 Five-Varable Karnaugh Maps
5.6 Other Used of Karnaugh Maps
5.7 Other Forms of Karnaugh Maps
Programmed Exercises
Problems
6 Quine-McCluskey Method
Objectives
Study Guide
6.1 Determination of Prime Implicants
6.2 The Prime Implicant Chart
6.3 Petrick's Method
6.4 Simplification of Incompletely Specified Functions
6.5 Simplification Using Map-Entered Variableds
6.6 Conclusion
Programmde Exercise
Problems
7 Multi-Level Gate CirCuits
NAND and NOR Gates
Objectives
Study Guide
7.1 Multi-Level Gate Circuits
7.2 NAND and NOR Gates
7.3 Design of Two-Level Circrits Using NAND and NOR Gates
7.4 Design of Multi-Level NAND and NOR Gate Circuits
7.5 Circuit Conversion Using Alternative Gate Symbols
7.6 Delign of Two-Level,Multiple-Ortput Circuits
Determination of Essential Prime Implicants for
Multiple-Output Realization
7.7 Multiple-Output NAND and NRO Circuits
8 Combinational Circuit Design
and Simulation Using Gates
Objectives
Study Guide
8.1 Review of Combinational Circuit Design
8.2 Design of Corcuits with Limited Gate Fan-In
8.3 Gate Delays and Timing Diagrams
8.4 Hazards in Combinational Logic
8.5 Simultion and Testion of Logic Circuits
Problems
Design Problems
9 Multiplexers,Declders,and Programmable
Logic Devices
Objectives
Study Guide
9.1 Introduction
9.2 Multiplexers
9.3 Three-State Buffers
9.4 Decoders and Encoders
9.5 Read-Only Memories
9.6 Programmable Logic Devices
Programmable Logic Arrays
Programmable Array Logic
9.7 Complex Programmable Logic Devices
9.8 Field Programmable Gate Arrays
Decomposition of Switching Fumctions
Problems
10 Introduction to VHDL
Objetives
Study Guide
10.1 VHDL Description of Combinational Circuits
10.2 VHDL Models for Multplexers
10.3 VHDL Modules
Four-Bit Full Adder
10.4 Signals and Constants
10.5 Arrays
10.6 VHDL Operators
10.7 Packages and Libraries
10.8 IEEE Stanedard Logic
10.9 Compilation and Simulation of VHDL Code
Problems
11 Latches and Flip-Flops
Objectives
Study Guide
11.1 Introduction
11.2 Set-Reset Latch
11.3 Gated D Latch
11.4 Edge-Triggerde D Flip-Flop
11.5 S-R FLIP-Flop
11.6 J-K Flip-Flop
11.7 T Flip-Flop
11.8 Flip-Flops with Additional Inputs
11.9 Summary
Prlblems
Programmde Exercise
12 Registers and Counters
Objectives
Study Guide
12.1 Registers and Register Transfers
Parallel Adder with Accumulator
12.2 Shift Registers
12.3 Design of Binary Counters
12.4 Counters for Other Sequences
Counters Design Using D Flip-Flops
12.5 Counter Design Using S-R and J-K Filp-Flops
12.6 Derivation of Flip-Flop Input Equations-Summary
Problems
13 Analysis of Clocked Sequential Circuits
Objectives
Study Guide
13.1 A Sequential Parety Checker
13.2 Analysis by Signal Tracing and Timing Charts
13.3 State Tables and Graphs
Construction and Interpretation of Timing Charts
13.4 General Models for Sequential Circuits
Programmed Exercise
Problems
14 Derivation of State Graphs and Tables
Objebtives
Study Guide
14.1 Design of a Sequence Detector
14.2 More Complex Design Problems
14.3 Guidelines rlf Comstruction of State Graphs
14.4 Serial Data Code Conversion
14.5 Alphanumeric State Graph Notation
Programmed Exercises
Probleml
15 Reduction of State Tables
State Assignment
Objectives
Study Guide
15.1 Elimination of Redundant States
15.2 Equivalent States
15.3 Determination of State Equivalence Using an Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incmpletely Specified State Tables
15.6 Derivation of Flip-Folp Input Equations
15.7 Equivalent State Assignments
15.8 Guidelines for State Assignment
15.9 Using a One-Hot State Assignment
Problems
16 Sequential Circuit Design
Objectives
Study Guide
16.1 Summary of Design Procedure for Sequential Circuits
16.2 Design Example-Code Converter
16.3 Design of Iterative Circuits
Design of a Comparator
16.4 Design of Sequential Circuits Using ROMs and PLAs
16.5 Sequential Circuit Design Using CPLDs
16.6 Sequential Circuit Design Using FPGAs
16.7 Simulation and Testing of Sequrential Circuits
16.8 Overview of Computer-Aided Design
Design Problems
Additional Problems
17 VHDL for Sequential Logic
Objectives
Study Guide
17.1 Modeling Flip-Flops Using VHDL Processes
17.2 Modeling Registers and Counters Using VHDL Processes
17.3 Modeling Combinational Logic Using VHDL Processes
17.4 Modeling a Sequential Machine
17.5 Synthesis of VHDL Code
17.6 More about Processes and Sequential Statements
Problems
Simulation Prlblems
18 Circuits for Arithmetic Operations
Objectives
Study Guide
18.1 Serial Adder with Accumulator
18.2 Design of a Parallel Multiplier
18.3 Design of a Binary Divider
Programmed Exercises
Prlblems
19 State Machine Design with SM Charts
Objectives
Study Guide
19.1 State Machine Charts
19.2 Derivation of SM Charts
19.3 Realization of SM Charts
Problems
20 VHDL for Digital System Design
Objectives
Study Guide
20.1 VHDL Code for a Serial Adder
20.2 VHDL Code for a Binary Multiplier
20.3 VHDL Code for a Binary Divider
20.4 VHDL Code for a Dice Game Simulator
20.5 Concluding Remarks
Problems
Lab Design Problems
A Appendices
A MOS and COMS Logic
B VHDL Language Summary
C Proofs of Theorems
References
Answers to Selected Study Guide
Questions and Problems
Index
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