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计算机组织与结构：性能设计（第4版 英文版）
作者：（美）[W.斯托林斯]William Stallings著
出版社：清华大学出版社
出版时间：1997-01-01
ISBN：9787302024156
定价：¥43.00
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内容简介
内容简介作者使用Inte1Pentium和PowerPC作为运行实例，从而将当代的设计问题和计算机组织与结构的基础联系起来。本书仔细考察了新的总线内联结构，Cache存储器组织与协议，指令集体系与I/O体系。其主要特征为：PCI和Futurebus＋这两个最新的系统总线规范用作实例；扩充了Cache存储器的内容，其中包括对指令集和数据Cache的考虑及CaChe两个层次的运用；讨论了DRAM组织的重要进展；讨论了RAID技术；详细探讨了SCSI并行和P1394串行总线规范；探讨了多处理机系统中Cache的一致性和MESI协议：讨论了含有许多微处理机的并行组织。
作者简介
暂缺《计算机组织与结构：性能设计（第4版 英文版）》作者简介
目录
CONTENTS
PREFACE xi
PART 1 OVERVIEW
CHAPTER 1 Introduction
1.1 Organization and Architecture
1.2 Structure and Function
1.3 Outline of the Book
CHAPTER 2 Computer Evolution and Performance
2.1 A Brief History of Computers
2.2 Designing for Performance
2.3 Pentium and PowerPC Evolution
2.4 Recommended Reading
2.5 Problems
PART 11 THE COMPUTER SYSTEM
CHAPTbR 3 System Buses
3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Stmctures
3.4 Bus Interconnection
3.5 PCI
3.6 Futurebus+
3.7 Recommended Reading
3.8 Problems
APPENDIX 3A Timing Diagrams
CHAPTER 4 Internal Memory
4.1 Computer Memory System Overview
4.2 Semiconductor Main Memory
4.3 Cache Memory
4.4 Advanced DRAM Organization
4.5 Recommended Reading
4.6 Problems
Appendix 4A Performance Characteristics of Two-Level Memories
CHAPTER 5 External Memory
5.1 Magnetic Disk
5.2 RAID 161
5.3 Optical Memory
5.4 Magnetic Tape
5.5 Recommended Reading
5.6 Problems
CHAPTER 6 Inpu/Output
6.1 Extemal Devices
6.2 1/0 Modules
6.3 Frogrammed 1/0
6.4 Iterrupt-Driven 1/0
6.5 Direct Memory Access
6.6 1/0 Channels and Processors
6.7 The Extemal Interface
6.8 Recommended Reading
6.9 Problems
CHAPTER 7 Operating System Support
7.1 Operating System Overview
7.2 Scheduling
7.3 Memory Management
7.4 Recommended Reading
7.5 Problems
PART 111 THE CENTRAL PROCESSING UNIT
CHAPTER 8 Computer Arithmetic
8.1 The Arithmetic and Logic Unit (ALU)
8.2 Integer Representation
8.3 Integer Arithmetic
8.4 Floating-Point Representation
8.5 Floating-Point Arithmetic
8.6 Recommended Reading
8.7 Problems 305
APPENDIX 8A Number Systems
CHAPTER 9 Instruction Sets: Characteristics and Functions
9.1 Machine Instruction Characteristics
9.2 Types of Operands
9.3 Types of Operations
9.4 Assembly Language
9.5 Recommended Reading
9.6 Problems
APPENDIX 9A Stacks
APPENDIX 9B Little-, Big-, and Bi-Endian
CHAPTER 10 Instruction Sets: Addressing Modes and Formats
10.1 -Addressing
10.2 Instruction Formats
10.3 Recommended Reading
10.4 Problems
CHAPTER 11 CPU Structure and Function
11.1 Processor Organization
11.2 Register Organization
11.3 The Instruction Cycle
11.4 Instruction Pipelining
11.5 The Pentium Processor
11.6 The PowerPC Processor
11.7 Recommended Reading
11.8 Problems
CHAPTER 12 Reduced Instruction Set Computers (RISCs)
12.1 Instruction Execution Characteristics
12.2 The Use of a Large Register File
12.3 Compiler-Based Register Optimization
12.4 Reduced Instruction Set Architecture
12.5 RISC Pipelining
12.6 Motorola 88510
12.7 MIPS4650
12.8 The RISC versus CISC Controversy
12.9 Recommended Reading
12.10 Problems
CHAPTER 13 Superscalar Processors
13.1 Overview
13.2 Design Issues
13.3 PowerPC
13.4 Pentium
13.5 Recommended Reading
13.6 Problems
PART IV THE CONTROL UNIT
CHAPTER14 Control Unit Operation
14.1 Micro-operations
14.2 ControloftheCPU
14.3 Hardwired Implementation
14.4 Recommended Reading
14.5 Problems
CHAPTER 15 Microprograrnmed Control
15.1 Basic Concepts
15.2 Microinstruction Sequencing
15.3 Microinstruction Execution
15.4 TI8800
15.5 Applications of Microprogramming
15.6 Recommended Reading
15.7 Problems
PART V PARALLEL ORGANIZATION
CHAPTER 16 Parallel Processing
16.1 Multiprocessing
16.2 Cache Coherence and the MESI Protocol
16.3 Vector Computation
16.4 Parallel Processors
16.5 Recommended Reading
16.6 Problems
APPENDIX Digital Logic
A.l Boolean Algebra
A.2 Gates
A.3 Combinational Circuits
A.4 Sequential Circuits
A.6 Problems
Glossary
References
Index
PREFACE xi
PART 1 OVERVIEW
CHAPTER 1 Introduction
1.1 Organization and Architecture
1.2 Structure and Function
1.3 Outline of the Book
CHAPTER 2 Computer Evolution and Performance
2.1 A Brief History of Computers
2.2 Designing for Performance
2.3 Pentium and PowerPC Evolution
2.4 Recommended Reading
2.5 Problems
PART 11 THE COMPUTER SYSTEM
CHAPTbR 3 System Buses
3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Stmctures
3.4 Bus Interconnection
3.5 PCI
3.6 Futurebus+
3.7 Recommended Reading
3.8 Problems
APPENDIX 3A Timing Diagrams
CHAPTER 4 Internal Memory
4.1 Computer Memory System Overview
4.2 Semiconductor Main Memory
4.3 Cache Memory
4.4 Advanced DRAM Organization
4.5 Recommended Reading
4.6 Problems
Appendix 4A Performance Characteristics of Two-Level Memories
CHAPTER 5 External Memory
5.1 Magnetic Disk
5.2 RAID 161
5.3 Optical Memory
5.4 Magnetic Tape
5.5 Recommended Reading
5.6 Problems
CHAPTER 6 Inpu/Output
6.1 Extemal Devices
6.2 1/0 Modules
6.3 Frogrammed 1/0
6.4 Iterrupt-Driven 1/0
6.5 Direct Memory Access
6.6 1/0 Channels and Processors
6.7 The Extemal Interface
6.8 Recommended Reading
6.9 Problems
CHAPTER 7 Operating System Support
7.1 Operating System Overview
7.2 Scheduling
7.3 Memory Management
7.4 Recommended Reading
7.5 Problems
PART 111 THE CENTRAL PROCESSING UNIT
CHAPTER 8 Computer Arithmetic
8.1 The Arithmetic and Logic Unit (ALU)
8.2 Integer Representation
8.3 Integer Arithmetic
8.4 Floating-Point Representation
8.5 Floating-Point Arithmetic
8.6 Recommended Reading
8.7 Problems 305
APPENDIX 8A Number Systems
CHAPTER 9 Instruction Sets: Characteristics and Functions
9.1 Machine Instruction Characteristics
9.2 Types of Operands
9.3 Types of Operations
9.4 Assembly Language
9.5 Recommended Reading
9.6 Problems
APPENDIX 9A Stacks
APPENDIX 9B Little-, Big-, and Bi-Endian
CHAPTER 10 Instruction Sets: Addressing Modes and Formats
10.1 -Addressing
10.2 Instruction Formats
10.3 Recommended Reading
10.4 Problems
CHAPTER 11 CPU Structure and Function
11.1 Processor Organization
11.2 Register Organization
11.3 The Instruction Cycle
11.4 Instruction Pipelining
11.5 The Pentium Processor
11.6 The PowerPC Processor
11.7 Recommended Reading
11.8 Problems
CHAPTER 12 Reduced Instruction Set Computers (RISCs)
12.1 Instruction Execution Characteristics
12.2 The Use of a Large Register File
12.3 Compiler-Based Register Optimization
12.4 Reduced Instruction Set Architecture
12.5 RISC Pipelining
12.6 Motorola 88510
12.7 MIPS4650
12.8 The RISC versus CISC Controversy
12.9 Recommended Reading
12.10 Problems
CHAPTER 13 Superscalar Processors
13.1 Overview
13.2 Design Issues
13.3 PowerPC
13.4 Pentium
13.5 Recommended Reading
13.6 Problems
PART IV THE CONTROL UNIT
CHAPTER14 Control Unit Operation
14.1 Micro-operations
14.2 ControloftheCPU
14.3 Hardwired Implementation
14.4 Recommended Reading
14.5 Problems
CHAPTER 15 Microprograrnmed Control
15.1 Basic Concepts
15.2 Microinstruction Sequencing
15.3 Microinstruction Execution
15.4 TI8800
15.5 Applications of Microprogramming
15.6 Recommended Reading
15.7 Problems
PART V PARALLEL ORGANIZATION
CHAPTER 16 Parallel Processing
16.1 Multiprocessing
16.2 Cache Coherence and the MESI Protocol
16.3 Vector Computation
16.4 Parallel Processors
16.5 Recommended Reading
16.6 Problems
APPENDIX Digital Logic
A.l Boolean Algebra
A.2 Gates
A.3 Combinational Circuits
A.4 Sequential Circuits
A.6 Problems
Glossary
References
Index
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