书籍详情
ASIC完备指南（影印版）
作者：Nigel Horspool，Peter Gorman编著
出版社：清华大学出版社
出版时间：2002-11-01
ISBN：9787302060574
定价：¥32.00
购买这本书可以去
内容简介
本书涵盖了专用集成电路（ASIC）设计的主要关键问题。详细讲述了ASIC设计各主要阶段关键的技术问题和可能遇到的组织管理问题。其中，技术上着重介绍了设计复用、高质量设计、编码技巧和综合指导原则。在管理方面主要讲述了项目组的组建，项目实施的规划，如何减少风险以及如何处理和ASIC厂商之间的关系等等。本书所描述的技术和方法学可以显著缩短ASIC设计周期，提高设计质量。既适合ASIC设计工程师，也适合ASIC项目负责人阅读。对于想要了解ASIC设计流程的读者，也有很好的借鉴意义。
作者简介
暂缺《ASIC完备指南（影印版）》作者简介
目录
Preface
Acknowledgments
Chapter 1 Phases of and ASIC Project
1.1 Introduction
1.2 List of Phases
1.3 Prestudy Phase
1.4 Top-Level Design Phase
1.5 Module Specification Phase
1.5.1 Tasks for the Bulk of the Team
1.5.2 Other Tasks
1.6 Module Design
1.6.1 Tasks for the Bulk of the Team
1.6.2 Other Tasks
1.7 Subsystem Simulation
1.7.1 Tasks for the Subsystem Simulation Team
1.7.2 Project Leader Tasks
1.8 System Simulation/Synthesis
1.8.1 Tasks for the System Simulation Team
1.8.2 Tasks for the Synthesis Team
1.8.3 Project Leader Tasks
1.9 Layout and the Backend Phase
1.10 Postlayout Simulation/Synthesis
1.11 ASIC Sign-Off
1.12 Preparation for Testing Silicon
1.13 Testing of Silicon
1.13.1 Project Leader Tasks
1.14 Summary
Chapter 2 Design Reuse and System-on-a-Chip Designs
2.1 Introduction
2.2 Reuse Documentation
2.2.1 Functional Overview
2.2.2 Interface Description
2.2.3 Implementation Details
2.2.4 Timing Diagrams
2.2.5 Test Methodology
2.2.6 Clocking Strategy
2.2.7 Source Code Control Strategy
2.2.8 Synthesis/Layout Approach
2.2.9 Module Validation Approach
2.2.10 Programmer's Reference Guide
2.3 Tips and Guidelines for Reuse
2.3.1 Company Standards
2.3.2 Coding Style
2.3.3 Generics and Constants
2.3.4 Clock Domains,Synchronous Design,Registers and Latches
2.3.5 Use of Standard Internal Buses
2.3.6 CPU-Addressable Registers
2.3.7 Technology Specifics
2.3.8 Verification,Testbenches and Debugging
2.3.9 VHDLversus Verilog
2.3.10 Live Documentation
2.3.11 Reviewing
2.4 SoC and Third-Party IP Integration
2.4.1 Developing In-House versus Sourcing Externally
2.4.2 Where to Source IP
2.4.3 Reducing the Risk with Parallel Third-Party IP Development
2.4.4 Issues with Third-Party IP
2.4.5 Processor and DSP Cores
2.5 System-Level Design Languages
2.6 Virtual Socket Interface Alliance
2.7 Summary
Chapter 3 A Quality Design Approach
3.1 Introduction
3.2 Project Design Documentation
3.2.1 Specifications
3.2.2 Hierarchy Diagram
3.2.3 Design Route Document
3.2.4 Module Documentation
3.2.5 The Test Approach Document
3.3 Reviews
3.3.1 Review of the Architecture Specification/Register Specifications
3.4 Module Design and Reviewing
3.4.1 Module Specification
3.4.2 Module Design Phase
3.4.3 Module Coding Phase
3.4.4 Module Simulation/Synthesis Phase
3.5 Quality System Simulations
3.6 Review Checklists
3.6.1 Specification Review Checklist
3.6.2 Design Documentation Review Checklist
3.6.3 Coding Phase Review Checklist
3.7 Summary
Chapter 4 Tips and Guidelines
4.1 Introduction
4.2 General Coding Guidelines
4.2.1 Simplicity
4.2.2 User-Defined Types and Complex Data Types
4.2.3 Naming Conventions
4.2.4 Constants
4.2.5 Use of Comments
4.2.6 Indentation
4.2.7 Ordering I/O Signals and Variable Declarations
4.2.8 Consistent Logic Assertion Levels
4.2.9 Use of Hierarchy and Design Partitioning
4.2.10 Unused States in State Machines
4.2.11 Glitch Sensitivity
4.2.12 Modular Interfaces
4.3 Coding for Synthesis
4.3.1 Inferred Latches
4.3.2 Sensitivity Lists
4.3.3 Registering Module Outputs
4.3.4 Reset Values on Registered Signals
4.3.5 State Machine Coding Styles
4.3.6 Multiplexers and Priority
4.3.7 Resource Sharing
4.3.8 Constructs That Will Not Synthesize
4.4 Coding for Testablity
4.4.1 Coding for Functional Simulation/Functional Verification
4.4.2 Scan-Text Issues
4.5 Coding for Multiple Clock Domains
4.5.1 Use of Multiple Clocks
4.5.2 Crossing Clock Boundaries
4.6 Summary
Chapter 5 ASIC Simulation and Testbenches
5.1 Introduction
5.2 Quality Testbenches
5.2.1 Generating Input Stimuli
5.2.2 Running the Tests
5.2.3 Comparing and Logging the Results
5.3 Simulation Strategy
5.3.1 Software Hierarchy
5.3.2 The Software Driver Testbench
5.3.3 C Model Cosimulation
5.3.4 Co-Verification Tool
5.3.5 Converting the C Code
5.4 Extending the Simulation Strategy
5.5 Reducing Top-Level Simulation Run Times
5.5.1 Increasing Workstation Performance
5.5.2 Changing Simulation Tools
5.5.3 Analysis of Simulation Statement Executions
5.5.4 Preloading RAMs
5.5.5 Usig Behavioral Models/Test Modes
5.5.6 Running Tests in Batch Mode
5.6 Speeding Up Debugging
5.6.1 Saving Simulation Snapshots
5.6.2 Source Code Debugging
5.7 Different Types of Testing
5.7.1 Module Testing
5.7.2 Subsystem Testing
5.7.3 Chip-Level Testing
5.7.4 Gate-Level Testing
5.7.5 Postlayout Testing
5.7.6 Board-Level Testing
5.8 Generation of ASIC Test Vectors
5.9 Summary
Chapter 6 Synthesis
6.1 Introduction
6.2 The General Principle
6.3 Top-Down versus Bottom-Up Synthesis
6.4 Physical Synthesis Tools
6.5 Scripts versus GUIs
6.6 Common Steps in Synthesis Scripts
6.6.1 Sample Script Action Sequence
6.6.2 Sample Scripts
6.7 Directory Structures
6.8 Special Cells
6.8.1 Handling Memory Cells
6.8.2 I/O Cells
6.8.3 Other Special Cells
6.9 Miscellaneous Synthesis Terms,Concepts and Issues
6.9.1 Timing Paths
6.9.2 Latches versus Flip-Flops
6.9.3 Timing Margins/Time Budgeting
6.9.4 Characterize and Compile
6.9.5 Overconstraining Designs
6.9.6 Grouping and Weighting
6.9.7 Flattening
6.9.8 dont_touch Attributes
6.9.9 Bladk Boxing
6.10 Managing Multiple Clock Domains
6.10.1 Isolate the Asynchronous Interfaces
6.10.2 Identify Synchronizing Flip-Flops with Unique Names
6.10.3 Set False Paths Across Known Asynchronous Boundaries
6.11 Managing Late Changes to the Netlist
6.11.1 Complete Resynthesis
6.11.2 Partial Resynthesis
6.11.3 Editing the Gate-Level Netlist
6.12 Summary
Chapter 7 Quality Framework
7.1 Introduction
7.2 The Directory Structure
7.2.1 engineer_work_area
7.2.2 reference_files
7.2.3 top_level_simulations
7.2.4 release_area
7.2.5 source Control
7.2.6 Synthesis Directory
7.2.7 Templates
7.3 Documentation Storage
7.4 Freezing Documents and Controlled Updates
7.5 Fault Report Database
7.6 Source Code Control
7.7 Makefiles/Simulation Scripts
7.8 Company-Defined Procedures
7.9 Summary
Chapter 8 Planning and Tracking ASIC Projects
8.1 Overview
8.2 Basic Planning Concepts
8.3 Process for Creating a Plan
8.3.1 Definition of Deliverables
8.3.2 Task Breakdown
8.3.3 Assigning Dependencies
8.3.4 Allocation of Resources
8.3.5 Refining the Plan
8.3.6 Reviewing the Plan
8.4 Tracking
8.4.1 Tracking Methods
8.5 Summary
Chapter 9 Reducing Project Risks
9.1 Introduction
9.2 Trade-Offs Between Functionlity,Performance,Cost and Timescales
9.3 Minimizing Development Risks
9.3.1 Selecting the Team
9.3.2 ASIC Architecture
9.3.3 High-Level Architectural Modeling
9.3.4 Interface Specifications
9.3.5 Managing Changing Design Requirements
9.3.6 Programmability
9.3.7 Regular Design Reviews
9.3.8 Early Trial Synthesis
9.3.9 Early Trial Layouts
9.4 Reducing the Risk of Design Bugs
9.4.1 Simulation
9.4.2 Emulation
9.4.3 FPGAs
9.4.4 Fast-Turnaround ASICs
9.4.5 Early Sign-Off
9.5 Risks in Meeting ASIC Vendor Criteria
9.5.1 Power Consumption Issues
9.5.2 Package/Pin-Out
9.6 Summary
Chapter 10 Dealing with the ASIC Vendor
10.1 Introduction
10.2 Using the Vendor's Expertse
10.3 Vendor Selection
10.3.1 RFQ Details
10.3.2 Vendor Comparisons
10.4 ASIC Vendor Services
10.5 Effect of the Vendor on Timescales
10.5.1 Layout
10.5.2 Provision of Engineering Samples
10.5.3 Production Chips
10.5.4 Liaison with the Vendor During the Project
10.6 Summary
Chapter 11 Motivation and People Management
11.1 Introcudtion
11.2 Managing Engineers with Different Experence Levels
11.3 Maslow's Hierarchy of Needs
11.3.1 Physiological Needs and Safety Needs
11.3.2 Social Contact
11.3.3 Self-Esteem
11.3.4 Self-Actualization
11.4 Getting to Know the Team
11.4.1 Different Personalities
11.4.2 Interacting with the Impulsive Type
11.4.3 Interacting with the Reflective Type
11.5 Goal Setting
11.6 Communicating Project Information
11.6.1 Project Meetings
11.6.2 Marketing Information
11.6.3 Competitors' Products
11.6.4 Highlighting the Importance of the Project to the Business
11.6.5 Show Enthusiasm and Have Fun
11.7 Training
11.7.1 Technical Training
11.7.2 Personal Training
11.7.3 Product/Design-Specific Training
11.8 Summary
Chapter 12 The Team
12.1 Introduction
12.2 The Project Leader/Project Manager
12.2.1 Technical Skills
12.2.2 People-and Team-Management Skills
12.3 The Wider Team
12.4 Key Roles Wighin the Team
12.4.1 System Architect
12.4.2 Tools Expert
12.4.3 Testbench Engineers
12.4.4 Team Leaders
12.5 Summary
Chapter 13 Project Manager Skills
13.1 Introduction
13.2 Running Meetings
13.3 Interviewing
13.4 Time Management
13.5 Summary
Chapter 14 Design Tools
14.1 Introduction
14.2 Hierarchy Tools
14.3 Input Tools
14.3.1 Text Editors
14.3.2 High-Level Entry Tools
14.4 Code Analysis Tools
14.5 Revision Management Tools
14.6 Testbench and Validation Tools
14.6.1 Testbench Tools
14.6.2 Code Coverage
14.6.3 Standard Simulators
14.6.4 Cycle-Based Simulators
14.6.5 Hardware Accelerators
14.6.6 Emulation
14.6.7 Cosimulation
14.6.8 Formal Verification
14.7 Synthesis Tools
14.8 Static-Timing Analyzers
14.9 Summary
Bibliography
About the Authors
Index
Acknowledgments
Chapter 1 Phases of and ASIC Project
1.1 Introduction
1.2 List of Phases
1.3 Prestudy Phase
1.4 Top-Level Design Phase
1.5 Module Specification Phase
1.5.1 Tasks for the Bulk of the Team
1.5.2 Other Tasks
1.6 Module Design
1.6.1 Tasks for the Bulk of the Team
1.6.2 Other Tasks
1.7 Subsystem Simulation
1.7.1 Tasks for the Subsystem Simulation Team
1.7.2 Project Leader Tasks
1.8 System Simulation/Synthesis
1.8.1 Tasks for the System Simulation Team
1.8.2 Tasks for the Synthesis Team
1.8.3 Project Leader Tasks
1.9 Layout and the Backend Phase
1.10 Postlayout Simulation/Synthesis
1.11 ASIC Sign-Off
1.12 Preparation for Testing Silicon
1.13 Testing of Silicon
1.13.1 Project Leader Tasks
1.14 Summary
Chapter 2 Design Reuse and System-on-a-Chip Designs
2.1 Introduction
2.2 Reuse Documentation
2.2.1 Functional Overview
2.2.2 Interface Description
2.2.3 Implementation Details
2.2.4 Timing Diagrams
2.2.5 Test Methodology
2.2.6 Clocking Strategy
2.2.7 Source Code Control Strategy
2.2.8 Synthesis/Layout Approach
2.2.9 Module Validation Approach
2.2.10 Programmer's Reference Guide
2.3 Tips and Guidelines for Reuse
2.3.1 Company Standards
2.3.2 Coding Style
2.3.3 Generics and Constants
2.3.4 Clock Domains,Synchronous Design,Registers and Latches
2.3.5 Use of Standard Internal Buses
2.3.6 CPU-Addressable Registers
2.3.7 Technology Specifics
2.3.8 Verification,Testbenches and Debugging
2.3.9 VHDLversus Verilog
2.3.10 Live Documentation
2.3.11 Reviewing
2.4 SoC and Third-Party IP Integration
2.4.1 Developing In-House versus Sourcing Externally
2.4.2 Where to Source IP
2.4.3 Reducing the Risk with Parallel Third-Party IP Development
2.4.4 Issues with Third-Party IP
2.4.5 Processor and DSP Cores
2.5 System-Level Design Languages
2.6 Virtual Socket Interface Alliance
2.7 Summary
Chapter 3 A Quality Design Approach
3.1 Introduction
3.2 Project Design Documentation
3.2.1 Specifications
3.2.2 Hierarchy Diagram
3.2.3 Design Route Document
3.2.4 Module Documentation
3.2.5 The Test Approach Document
3.3 Reviews
3.3.1 Review of the Architecture Specification/Register Specifications
3.4 Module Design and Reviewing
3.4.1 Module Specification
3.4.2 Module Design Phase
3.4.3 Module Coding Phase
3.4.4 Module Simulation/Synthesis Phase
3.5 Quality System Simulations
3.6 Review Checklists
3.6.1 Specification Review Checklist
3.6.2 Design Documentation Review Checklist
3.6.3 Coding Phase Review Checklist
3.7 Summary
Chapter 4 Tips and Guidelines
4.1 Introduction
4.2 General Coding Guidelines
4.2.1 Simplicity
4.2.2 User-Defined Types and Complex Data Types
4.2.3 Naming Conventions
4.2.4 Constants
4.2.5 Use of Comments
4.2.6 Indentation
4.2.7 Ordering I/O Signals and Variable Declarations
4.2.8 Consistent Logic Assertion Levels
4.2.9 Use of Hierarchy and Design Partitioning
4.2.10 Unused States in State Machines
4.2.11 Glitch Sensitivity
4.2.12 Modular Interfaces
4.3 Coding for Synthesis
4.3.1 Inferred Latches
4.3.2 Sensitivity Lists
4.3.3 Registering Module Outputs
4.3.4 Reset Values on Registered Signals
4.3.5 State Machine Coding Styles
4.3.6 Multiplexers and Priority
4.3.7 Resource Sharing
4.3.8 Constructs That Will Not Synthesize
4.4 Coding for Testablity
4.4.1 Coding for Functional Simulation/Functional Verification
4.4.2 Scan-Text Issues
4.5 Coding for Multiple Clock Domains
4.5.1 Use of Multiple Clocks
4.5.2 Crossing Clock Boundaries
4.6 Summary
Chapter 5 ASIC Simulation and Testbenches
5.1 Introduction
5.2 Quality Testbenches
5.2.1 Generating Input Stimuli
5.2.2 Running the Tests
5.2.3 Comparing and Logging the Results
5.3 Simulation Strategy
5.3.1 Software Hierarchy
5.3.2 The Software Driver Testbench
5.3.3 C Model Cosimulation
5.3.4 Co-Verification Tool
5.3.5 Converting the C Code
5.4 Extending the Simulation Strategy
5.5 Reducing Top-Level Simulation Run Times
5.5.1 Increasing Workstation Performance
5.5.2 Changing Simulation Tools
5.5.3 Analysis of Simulation Statement Executions
5.5.4 Preloading RAMs
5.5.5 Usig Behavioral Models/Test Modes
5.5.6 Running Tests in Batch Mode
5.6 Speeding Up Debugging
5.6.1 Saving Simulation Snapshots
5.6.2 Source Code Debugging
5.7 Different Types of Testing
5.7.1 Module Testing
5.7.2 Subsystem Testing
5.7.3 Chip-Level Testing
5.7.4 Gate-Level Testing
5.7.5 Postlayout Testing
5.7.6 Board-Level Testing
5.8 Generation of ASIC Test Vectors
5.9 Summary
Chapter 6 Synthesis
6.1 Introduction
6.2 The General Principle
6.3 Top-Down versus Bottom-Up Synthesis
6.4 Physical Synthesis Tools
6.5 Scripts versus GUIs
6.6 Common Steps in Synthesis Scripts
6.6.1 Sample Script Action Sequence
6.6.2 Sample Scripts
6.7 Directory Structures
6.8 Special Cells
6.8.1 Handling Memory Cells
6.8.2 I/O Cells
6.8.3 Other Special Cells
6.9 Miscellaneous Synthesis Terms,Concepts and Issues
6.9.1 Timing Paths
6.9.2 Latches versus Flip-Flops
6.9.3 Timing Margins/Time Budgeting
6.9.4 Characterize and Compile
6.9.5 Overconstraining Designs
6.9.6 Grouping and Weighting
6.9.7 Flattening
6.9.8 dont_touch Attributes
6.9.9 Bladk Boxing
6.10 Managing Multiple Clock Domains
6.10.1 Isolate the Asynchronous Interfaces
6.10.2 Identify Synchronizing Flip-Flops with Unique Names
6.10.3 Set False Paths Across Known Asynchronous Boundaries
6.11 Managing Late Changes to the Netlist
6.11.1 Complete Resynthesis
6.11.2 Partial Resynthesis
6.11.3 Editing the Gate-Level Netlist
6.12 Summary
Chapter 7 Quality Framework
7.1 Introduction
7.2 The Directory Structure
7.2.1 engineer_work_area
7.2.2 reference_files
7.2.3 top_level_simulations
7.2.4 release_area
7.2.5 source Control
7.2.6 Synthesis Directory
7.2.7 Templates
7.3 Documentation Storage
7.4 Freezing Documents and Controlled Updates
7.5 Fault Report Database
7.6 Source Code Control
7.7 Makefiles/Simulation Scripts
7.8 Company-Defined Procedures
7.9 Summary
Chapter 8 Planning and Tracking ASIC Projects
8.1 Overview
8.2 Basic Planning Concepts
8.3 Process for Creating a Plan
8.3.1 Definition of Deliverables
8.3.2 Task Breakdown
8.3.3 Assigning Dependencies
8.3.4 Allocation of Resources
8.3.5 Refining the Plan
8.3.6 Reviewing the Plan
8.4 Tracking
8.4.1 Tracking Methods
8.5 Summary
Chapter 9 Reducing Project Risks
9.1 Introduction
9.2 Trade-Offs Between Functionlity,Performance,Cost and Timescales
9.3 Minimizing Development Risks
9.3.1 Selecting the Team
9.3.2 ASIC Architecture
9.3.3 High-Level Architectural Modeling
9.3.4 Interface Specifications
9.3.5 Managing Changing Design Requirements
9.3.6 Programmability
9.3.7 Regular Design Reviews
9.3.8 Early Trial Synthesis
9.3.9 Early Trial Layouts
9.4 Reducing the Risk of Design Bugs
9.4.1 Simulation
9.4.2 Emulation
9.4.3 FPGAs
9.4.4 Fast-Turnaround ASICs
9.4.5 Early Sign-Off
9.5 Risks in Meeting ASIC Vendor Criteria
9.5.1 Power Consumption Issues
9.5.2 Package/Pin-Out
9.6 Summary
Chapter 10 Dealing with the ASIC Vendor
10.1 Introduction
10.2 Using the Vendor's Expertse
10.3 Vendor Selection
10.3.1 RFQ Details
10.3.2 Vendor Comparisons
10.4 ASIC Vendor Services
10.5 Effect of the Vendor on Timescales
10.5.1 Layout
10.5.2 Provision of Engineering Samples
10.5.3 Production Chips
10.5.4 Liaison with the Vendor During the Project
10.6 Summary
Chapter 11 Motivation and People Management
11.1 Introcudtion
11.2 Managing Engineers with Different Experence Levels
11.3 Maslow's Hierarchy of Needs
11.3.1 Physiological Needs and Safety Needs
11.3.2 Social Contact
11.3.3 Self-Esteem
11.3.4 Self-Actualization
11.4 Getting to Know the Team
11.4.1 Different Personalities
11.4.2 Interacting with the Impulsive Type
11.4.3 Interacting with the Reflective Type
11.5 Goal Setting
11.6 Communicating Project Information
11.6.1 Project Meetings
11.6.2 Marketing Information
11.6.3 Competitors' Products
11.6.4 Highlighting the Importance of the Project to the Business
11.6.5 Show Enthusiasm and Have Fun
11.7 Training
11.7.1 Technical Training
11.7.2 Personal Training
11.7.3 Product/Design-Specific Training
11.8 Summary
Chapter 12 The Team
12.1 Introduction
12.2 The Project Leader/Project Manager
12.2.1 Technical Skills
12.2.2 People-and Team-Management Skills
12.3 The Wider Team
12.4 Key Roles Wighin the Team
12.4.1 System Architect
12.4.2 Tools Expert
12.4.3 Testbench Engineers
12.4.4 Team Leaders
12.5 Summary
Chapter 13 Project Manager Skills
13.1 Introduction
13.2 Running Meetings
13.3 Interviewing
13.4 Time Management
13.5 Summary
Chapter 14 Design Tools
14.1 Introduction
14.2 Hierarchy Tools
14.3 Input Tools
14.3.1 Text Editors
14.3.2 High-Level Entry Tools
14.4 Code Analysis Tools
14.5 Revision Management Tools
14.6 Testbench and Validation Tools
14.6.1 Testbench Tools
14.6.2 Code Coverage
14.6.3 Standard Simulators
14.6.4 Cycle-Based Simulators
14.6.5 Hardware Accelerators
14.6.6 Emulation
14.6.7 Cosimulation
14.6.8 Formal Verification
14.7 Synthesis Tools
14.8 Static-Timing Analyzers
14.9 Summary
Bibliography
About the Authors
Index
猜您喜欢
