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财务报表解释（ACCA财务管理证书 模块A）
作者：张新民，武艳辉译；张新民译
出版社：中信出版社
出版时间：2002-09-01
ISBN：9787800733857
定价：¥56.00
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内容简介
财务管理证书（DFM）是ACCA专为企业经理人和财务管理人员设计的国际化的权威资格证书。本证书共包括四门课程：1.《财务报表解释》 2.《绩效管理》 3.《财务战略》 4.《风险管理》全面、系统、深入地介绍了针对公司外部人员财务报表的制度框架、原则和方法。系统地学完本书之后，读者将能够： ·描述外部财务报表的作用、功能以及准备财务报表的制度框架 ·解释一般公认会计原则项下的会计原则和制度 ·运用简单的计算模式解释一些基本财务报表的格式、算法、意义、内容等 ·描述公司年报中财务报表以外部分附属信息的作用 ·运用财务报表分析，特别是财务和会计比率，来计算、解释并评估财务经营情况、财务状况及其适变性
作者简介
张新民，对外经济贸易大学国际工商管理学院院长，会计学教授。1962年12月生，管理学博士，企业财务状况质量分析理论的创立者，中国会计学会理事，中国对外经济贸易会计学会常务理事。中国大陆高等院校中惟一一位拥有英国特许公认会师（ACCA）资格的现职会计学教授。在《会计研究》、《财务与会计》等专业刊物发表论文30余篇；出版专著《企业财务状况质量分析理论研究》（2001年12月）、《企业财务报表分析》（2001年2月）、《企业财务分析》（2000年10月）、《看报表、选股票》（2001年5月）、《中国会计热点问题》（1996年5月）；主编《会计学原理》（1999年2月）、《税务会计》（1997年9月）、《中级会计英语》（1995年9月）等多部专业书籍；主译英国特许公认会计师协会著作《高级会计实务》（1996年5月）。2000年3月、2001年3月，带领对外经济贸易大学研究生代表队，代表中国赴葡萄牙参加国际企业管理挑战战赛（CMC）国际总决赛，两次获得世界冠军。主要研究与教学领域：会计学理论与实务，企业财务分析——质量分析与管理透视，资产管理研究等。武艳辉，安徽省合肥市人。2000年毕业于原中国金融学院。现为对外经济贸易大学工商管理学院会计学硕士研究生。在《金融会计》、《对外经济贸易大学学报》等刊物上公开发表学术论文数篇。参编《上市公司财务报表分析》等书。
目录
Preface xi
CHAPTER l Digital Concepts and Number Systems
Introduction l
l.l Digital and Analog: Basic Concepts 1
l.2 Some History of Digital Systems 4
l.3 Impact of Digital Technology on Society 6
1.4 Defining the Problem, an Introduction to Algorithms 7
1.5 Digital Systems Overview 9
l.6 Introduction to Number Systems 9
l.7 Positional Number Systems 10
1.7.l Decima1Numbers l0
l.7.2 Binary Numbers 11
l.7.3 Octal Numbers l2
1.7.4 Hexadecimal Numbers 12
1.7.5 Counting in Baser 13
l.8 Number System Conversion l4
1.8.l Binary to Hexadecimal Conversion 15
l.8.2 Hexadecimal and Octal to Binary Conversion 16
l.8.3 Binary to Decimal Conversion l6
1.8.4 Successive Division Radix Conversion l7
1.8.5 Fractional Radix Conversion, Successive Multiplication 18
l.8.6 Radix Conversion Algorithm 20
l.8.7 Decimal to Any Radix 2l
l.8.8 Any Radix to Decimal 23
l.9 Binary Codes 23
l.9.l Natural Binary Coded Decimal 23
l.9.2 Binary Codes (Weighted) 24
1.9.3 BCD Self Complementing Codes 25
l.9.4 Unit Distance Code 26
1.9.5 Alphanumeric Codes 28
l.9.6 Signed Number Binary Codes 28
l.9.7 Signed Magnitude Codes 28
l.9.8 Complement Codes 29
l.l0 Arithmetic 32
l.l0.l Binary Arithmetic 32
l.l0.2 Binary Arithmetic Using Complement Codes 35
1.l0.3 Hexadecimal Arithmetic 38
Summary 42
References 43
Glossary 44
Questions and Problems 45
CHAPTER 2 Boolean Switching Algebra
Introduction 48
2.1 Binary Logic Functions 48
2.1.l IEEE Logic Symbols 54
2.l.2 Functions, Symbols, and Truth Tables 55
2.2 Switching Algebra 57
2.2.l Equivalence 58
2.2.2 Closure 58
2.2.3 Identity 59
2.2.4 Associative Properties 59
2.2.5 Distributive Properties 6l
2.2.6 Commutative Properties 62
2.2.7 Complement Property 62
2.2.8 Duality Property 62
2.2.9 Absorption Property 62
2.2.l0 Idempotency Property 63
2.2.ll Binary Variables and Constants 63
2.2.12 DeMorgan's Theorems
2.3 Functionally Complete Operation Sets 68
2.4 Reduction of Switching Equations Using Boolean Algebra 70
2.5 Realization of Switching Functions 73
2.5.1 Conversion of Switching Functions to Logic Diagrams 73
2.5.2 Converting Logic Diagrams to Switching Equations 77
Summary 80
References 80
Glossary 81
Questions and Problems 82
CHAPTER 3 Principles of Combinational Logic
Introduction 84
3.l Definition of Combinational Logic 84
3.l.l Problem Statements to Truth Tables 85
3.1.2 Deriving Switching Equations 89
3.2 Canonical Forms 91
3.3 Generation of Switching Equations from Truth Tables 93
3.4 Karnaugh Maps 96
3.4.l Three-and Four-Variable Karnaugh Maps 97
3.4.2 Five-and Sis-Variable Karnaugh Maps l07
3.4.3 Simplification Using Five-Variable Karnaugh Maps 109
3.4.4 Simplification Using Six-Variable Karnaugh Maps 112
3.4.5 Incompletely Specified Functions (Don't Care Terms) 1l3
3.4.6 Simplifying Maxterm Equations ll7
3.5 Quine - McClusky Minimization Technique l20
3.5.1 Quine-McClusky Using Don't Care Terms 123
3.5.2 Reduced Prime Imp1icant Tables l25
3.6 Map-Entered Variables l29
3.7 Mixed Logic Combinational Circuits l35
3.7.1 Logic Symbols l36
3.7.2 Conversion to Bubble Logic 140
3.7.3 Synthesizing Switching Functions Using Bubble Notation l42
3.8 Multiple Output Functions l46
Summary l49
References 150
Glossary l50
Questions and Problems l5l
CHAPTER 4 Analysis and Design of Combinational Logic
Introduction l56
4.1 General Approach to Combinational Logic Design l56
4.2 Introduction to Digital Integrated Circuits l64
4.3 Decoders l71
4.3.l BCD Decoders l8l
4.4 Encoders l85
4.5 Digital Multiplexers l90
4.5.l Using Multiplexers as Boolean Function Generators l94
4.6 Adders and Subtractors 20l
4.6.l Cascading Full-Adders 205
4.6.2 Look-Ahead Carry 206
4.6.3 MSI Adders 207
4.6.4 Using MSI Adders as Subtractors 208
4.6.5 Using an MSI Adder as a BCD to Excess-3 Code Converter 211
4.6.6 BCD Adder 212
4.7 Binary Comparators 215
4.8 Arithmetic Logic Units 222
4.9 Array Multipliers 225
4.10 Tristate Buffers 228
4.l1 Combinational Logic Hazards 23l
4.ll.l Static Hazards 232
4.ll.2 Dynamic Hazards 236
Summary 237
References 237
Glossary 238
Questions and Problems 239
CHAPTER 5 Flip-Flops, Simple Counters, and Registers
Introduction 243
5.1 Sequential Circuit Models 243
5.2 Flip-Flops 248
5.2.l Flip-Flop Logic Symbols, Function, and Triggering 248
5.3 Flip-F1op Timing Specifications 265
5.3.l Clock Parameters, Pulse Width, and Skew 265
5.3.2 Flip-Flop Timing, Setup, Hold, and Delay 267
5.3.3 Flip-Flop Metastability 268
5.4 Simple Counters 27l
5.4.l Divide by 2, 4, and 8 Counters (Asynchronous) 272
5.4.2 Johnson Counter (Synchronous) 274
5.4.3 Ring Counter (synchronous) 275
5.5 MSI Integrated Circuit Counters 276
5.5.1 MSI Asynchronous Counters 277
5.5.2 MSI Synchronous Counters 279
5.5.3 Contro1 Signal Generation by Decoding Counter Outputs 283
5.5.4 A Counter Application: Digital Clock 287
5.5.5 IEEE Standard Symbols for MSI Counters 29l
5.6 Registers 295
5.6.l Registers Data Input and Output 295
5.6.2 Tristate Registers 300
5.6.3 Registers Connected to a Common Data Bus 305
5.6.4 R6gister Transfer Timing Considerations 3l0
Summary 312
References 313
Glossary 3l4
Questions and Problems 3l6
CHAPTER 6 Introduction to Sequential Circuits
Introduction 322
6.l Mea1y and Moore Models 322
6.2 State Machine Notation 323
6.2.l Present State, Next State 324
6.2.2 State Diagram 324
6.2.3 State Table 328
6.2.4 Transition Table 329
6.2.5 Excitation Table and Equations 330
6.2.6 Excitation Realization Cost 336
6.3 Synchronous Sequential Circuit Analysis 339
6.3.l Analysis Principles 340
6.3.2 Analysis Examples 340
6.4 Construction of State Diagrams 348
6.4.l Up-Down Decade Counter 349
6.4.2 Sequence Detectors 349
6.4.3 Serial EX-3 to BCD Code Converter 354
6.5 Counter Design 356
6.5.l Modulo-8 Synchronous Counter 357
6.5.2 Up-Down Decade Counter Design 360
Summary 369
References 370
Glossary 370
Questions and Problems 37l
CHAPTER 7 Sequential Circuit Design
Introduction 375
7.l State Equivalence 375
7.2 State Reduction 376
7.2.l Equivalence Classes 376
7.2.2 Implication Charts 378
7.3 State Reduction of Incompletely Specified State Tables 384
7.3.1 Merger Graphs 386
7.4 State Assignment Techniques 389
7.4.1 State Assignment Permutations 390
7.4.2 State Assignment Algorithm 392
7.4.3 Implication Graph 396
7.5 A1gorithm State Machines 399
7.5.l ASM Symbols 399
7.5.2 Elapsed Time Measurement, an ASM Design Example 404
7.6 Linked Sequential Machines 4l3
7.6.l Computer Simulator and Graphic Plotter Interface,
a Linked Sequential Machine Design Example 4l5
Summary 432
References 433
Glossary 433
Questions and Problems 434
CHAPTER 8 Asynchronous Sequential Circuits
Introduction to Asynchronous Sequential Machines
8.l Fundamental and Pulse Mode Asynchronous Sequential Machines 442
8.2 Analysis of Asynchronous Sequential Machines 444
8.3 Deriving Flow Tables 452
8.4 State Assignment 456
8.4.l Races and Cycles 456
8.4.2 Shared Row State Assignment 458
8.4.3 Multiple Row State Assignment 460
8.4.4 One Hot State Assignment 46l
8.5 Asynchronous Design Problems 462
8.5.l Asynchronous Design Problem l 463
8.5.2 Asynchronous Design Problem 2 465
8.6 Data Synchronizers 470
8.6.l Interface Protocol Asynchronous Cell 472
8.7 Mixed Operating Mode Asynchronous Circuits 474
Summary 477
References 478
Glossary 479
Questions and Problems 480
CHAPTER 9 Programmable Logic and Memory
Introduction 485
9.1 Memory 486
9.1.1 ROM, PROM, and EPROM 486,
9.2 Using an EPROM to Realize a Sequential Circuit 49l
9.3 Programmable Logic Devices 495
9.3.l Programmable Logic Array (PLA) 496
9.3.2 Programmable Array Logic 498
9.3.3 Designing an Up-Down Decade Counter Using a PAL 502
9.3.4 Generic Array Logic 507
9.3.5 Designing a Synchronous Sequential Circuit Using a GAL 509
9.4 Erasable Programmable Logic Devices 5l4
9.4.l Altera EP600 EPLD 5l7
9.4.2 Sequential Circuit Realization Using an EP600 5l9
9.5 PLD Computer-Aided Design 523
9.5.l PLD Realization of Combinational Logic 525
9:5.2 Realizing Truth Tables Using a PLD Language 529
9.5.3 Realizing Flip-Flops Using a PLD Language 530
9.5.4 Realizing State Machines Using a PLD Language 530
9.6 Field Programmable Gate Arrays 534
9.6.l Xilinx FPGA 535
9.6.2 System Development Tools for the Xilinx FPGA 542
9.6.3 Xilinx Macro Library 543
9.6.4 Actel FPGA 543
Summary 549
References 550
Glossary 55l
Questions and Problems 552
CHAPTER l0 Digital Integrated Circuits
Introduction 556
l0.1 Diodes as Switches 556
l0.l.l Diode Gates 558
l0.2 Bipolar Transistor Switch 56l
l0.3 Diode Transistor Logic 562
l0.4 Evolution from DTL to TTL 563
10.5 Transistor--Transistor Logic 565
l0.5.l TTL Circuit Operation 567
l0.5.2 TTL Specifications 569
l0.5.3 TTL Subfamilies 573
l0.5.4 Schottky Junctions 578
l0.5.5 Comparison of TTL Subfamily Specifications 579
l0.5.6 Open Collector TTL Circuits 580
l0.5.7 Tristate TTL Devices 584
l0.5.8 Mixed TTL Subfamily Fan-Out 585
l0.5.9 Other TTL Circuits 587
l0.6 Emitter-Coupled Logic 590
l0.6.1 Emitter-Coupled Logic Circuit 590
l0.6.2 ECL Specifications 594
l0.6.3 ECL to TTL and TTL to ECL Interfacing 595
l0.7 Complementary Metal Oxide Semiconductor 597
l0.7.l Field Effect Transistors 597
l0.7.2 MOSFETs 603
l0.7.3 MOSFET Logic Gates 606
l0.7.4 CMOS Logic Gates 609
l0.7.5 Power Dissipation for High-Speed CMOS 6l2
l0.7.6 Propagation Delay for High-Speed CMOS 6l3
l0.7.7 CMOS Noise Margins 613
l0.7.8 CMOS Subfamilies 613
Summary 6l5
References 615
Glossary 616
Questions and Problems 617
Appendix l TTL Analysis Spice Exercise
Appendix 2 Answers to Odd-Numbered Questions and Problems
Index
CHAPTER l Digital Concepts and Number Systems
Introduction l
l.l Digital and Analog: Basic Concepts 1
l.2 Some History of Digital Systems 4
l.3 Impact of Digital Technology on Society 6
1.4 Defining the Problem, an Introduction to Algorithms 7
1.5 Digital Systems Overview 9
l.6 Introduction to Number Systems 9
l.7 Positional Number Systems 10
1.7.l Decima1Numbers l0
l.7.2 Binary Numbers 11
l.7.3 Octal Numbers l2
1.7.4 Hexadecimal Numbers 12
1.7.5 Counting in Baser 13
l.8 Number System Conversion l4
1.8.l Binary to Hexadecimal Conversion 15
l.8.2 Hexadecimal and Octal to Binary Conversion 16
l.8.3 Binary to Decimal Conversion l6
1.8.4 Successive Division Radix Conversion l7
1.8.5 Fractional Radix Conversion, Successive Multiplication 18
l.8.6 Radix Conversion Algorithm 20
l.8.7 Decimal to Any Radix 2l
l.8.8 Any Radix to Decimal 23
l.9 Binary Codes 23
l.9.l Natural Binary Coded Decimal 23
l.9.2 Binary Codes (Weighted) 24
1.9.3 BCD Self Complementing Codes 25
l.9.4 Unit Distance Code 26
1.9.5 Alphanumeric Codes 28
l.9.6 Signed Number Binary Codes 28
l.9.7 Signed Magnitude Codes 28
l.9.8 Complement Codes 29
l.l0 Arithmetic 32
l.l0.l Binary Arithmetic 32
l.l0.2 Binary Arithmetic Using Complement Codes 35
1.l0.3 Hexadecimal Arithmetic 38
Summary 42
References 43
Glossary 44
Questions and Problems 45
CHAPTER 2 Boolean Switching Algebra
Introduction 48
2.1 Binary Logic Functions 48
2.1.l IEEE Logic Symbols 54
2.l.2 Functions, Symbols, and Truth Tables 55
2.2 Switching Algebra 57
2.2.l Equivalence 58
2.2.2 Closure 58
2.2.3 Identity 59
2.2.4 Associative Properties 59
2.2.5 Distributive Properties 6l
2.2.6 Commutative Properties 62
2.2.7 Complement Property 62
2.2.8 Duality Property 62
2.2.9 Absorption Property 62
2.2.l0 Idempotency Property 63
2.2.ll Binary Variables and Constants 63
2.2.12 DeMorgan's Theorems
2.3 Functionally Complete Operation Sets 68
2.4 Reduction of Switching Equations Using Boolean Algebra 70
2.5 Realization of Switching Functions 73
2.5.1 Conversion of Switching Functions to Logic Diagrams 73
2.5.2 Converting Logic Diagrams to Switching Equations 77
Summary 80
References 80
Glossary 81
Questions and Problems 82
CHAPTER 3 Principles of Combinational Logic
Introduction 84
3.l Definition of Combinational Logic 84
3.l.l Problem Statements to Truth Tables 85
3.1.2 Deriving Switching Equations 89
3.2 Canonical Forms 91
3.3 Generation of Switching Equations from Truth Tables 93
3.4 Karnaugh Maps 96
3.4.l Three-and Four-Variable Karnaugh Maps 97
3.4.2 Five-and Sis-Variable Karnaugh Maps l07
3.4.3 Simplification Using Five-Variable Karnaugh Maps 109
3.4.4 Simplification Using Six-Variable Karnaugh Maps 112
3.4.5 Incompletely Specified Functions (Don't Care Terms) 1l3
3.4.6 Simplifying Maxterm Equations ll7
3.5 Quine - McClusky Minimization Technique l20
3.5.1 Quine-McClusky Using Don't Care Terms 123
3.5.2 Reduced Prime Imp1icant Tables l25
3.6 Map-Entered Variables l29
3.7 Mixed Logic Combinational Circuits l35
3.7.1 Logic Symbols l36
3.7.2 Conversion to Bubble Logic 140
3.7.3 Synthesizing Switching Functions Using Bubble Notation l42
3.8 Multiple Output Functions l46
Summary l49
References 150
Glossary l50
Questions and Problems l5l
CHAPTER 4 Analysis and Design of Combinational Logic
Introduction l56
4.1 General Approach to Combinational Logic Design l56
4.2 Introduction to Digital Integrated Circuits l64
4.3 Decoders l71
4.3.l BCD Decoders l8l
4.4 Encoders l85
4.5 Digital Multiplexers l90
4.5.l Using Multiplexers as Boolean Function Generators l94
4.6 Adders and Subtractors 20l
4.6.l Cascading Full-Adders 205
4.6.2 Look-Ahead Carry 206
4.6.3 MSI Adders 207
4.6.4 Using MSI Adders as Subtractors 208
4.6.5 Using an MSI Adder as a BCD to Excess-3 Code Converter 211
4.6.6 BCD Adder 212
4.7 Binary Comparators 215
4.8 Arithmetic Logic Units 222
4.9 Array Multipliers 225
4.10 Tristate Buffers 228
4.l1 Combinational Logic Hazards 23l
4.ll.l Static Hazards 232
4.ll.2 Dynamic Hazards 236
Summary 237
References 237
Glossary 238
Questions and Problems 239
CHAPTER 5 Flip-Flops, Simple Counters, and Registers
Introduction 243
5.1 Sequential Circuit Models 243
5.2 Flip-Flops 248
5.2.l Flip-Flop Logic Symbols, Function, and Triggering 248
5.3 Flip-F1op Timing Specifications 265
5.3.l Clock Parameters, Pulse Width, and Skew 265
5.3.2 Flip-Flop Timing, Setup, Hold, and Delay 267
5.3.3 Flip-Flop Metastability 268
5.4 Simple Counters 27l
5.4.l Divide by 2, 4, and 8 Counters (Asynchronous) 272
5.4.2 Johnson Counter (Synchronous) 274
5.4.3 Ring Counter (synchronous) 275
5.5 MSI Integrated Circuit Counters 276
5.5.1 MSI Asynchronous Counters 277
5.5.2 MSI Synchronous Counters 279
5.5.3 Contro1 Signal Generation by Decoding Counter Outputs 283
5.5.4 A Counter Application: Digital Clock 287
5.5.5 IEEE Standard Symbols for MSI Counters 29l
5.6 Registers 295
5.6.l Registers Data Input and Output 295
5.6.2 Tristate Registers 300
5.6.3 Registers Connected to a Common Data Bus 305
5.6.4 R6gister Transfer Timing Considerations 3l0
Summary 312
References 313
Glossary 3l4
Questions and Problems 3l6
CHAPTER 6 Introduction to Sequential Circuits
Introduction 322
6.l Mea1y and Moore Models 322
6.2 State Machine Notation 323
6.2.l Present State, Next State 324
6.2.2 State Diagram 324
6.2.3 State Table 328
6.2.4 Transition Table 329
6.2.5 Excitation Table and Equations 330
6.2.6 Excitation Realization Cost 336
6.3 Synchronous Sequential Circuit Analysis 339
6.3.l Analysis Principles 340
6.3.2 Analysis Examples 340
6.4 Construction of State Diagrams 348
6.4.l Up-Down Decade Counter 349
6.4.2 Sequence Detectors 349
6.4.3 Serial EX-3 to BCD Code Converter 354
6.5 Counter Design 356
6.5.l Modulo-8 Synchronous Counter 357
6.5.2 Up-Down Decade Counter Design 360
Summary 369
References 370
Glossary 370
Questions and Problems 37l
CHAPTER 7 Sequential Circuit Design
Introduction 375
7.l State Equivalence 375
7.2 State Reduction 376
7.2.l Equivalence Classes 376
7.2.2 Implication Charts 378
7.3 State Reduction of Incompletely Specified State Tables 384
7.3.1 Merger Graphs 386
7.4 State Assignment Techniques 389
7.4.1 State Assignment Permutations 390
7.4.2 State Assignment Algorithm 392
7.4.3 Implication Graph 396
7.5 A1gorithm State Machines 399
7.5.l ASM Symbols 399
7.5.2 Elapsed Time Measurement, an ASM Design Example 404
7.6 Linked Sequential Machines 4l3
7.6.l Computer Simulator and Graphic Plotter Interface,
a Linked Sequential Machine Design Example 4l5
Summary 432
References 433
Glossary 433
Questions and Problems 434
CHAPTER 8 Asynchronous Sequential Circuits
Introduction to Asynchronous Sequential Machines
8.l Fundamental and Pulse Mode Asynchronous Sequential Machines 442
8.2 Analysis of Asynchronous Sequential Machines 444
8.3 Deriving Flow Tables 452
8.4 State Assignment 456
8.4.l Races and Cycles 456
8.4.2 Shared Row State Assignment 458
8.4.3 Multiple Row State Assignment 460
8.4.4 One Hot State Assignment 46l
8.5 Asynchronous Design Problems 462
8.5.l Asynchronous Design Problem l 463
8.5.2 Asynchronous Design Problem 2 465
8.6 Data Synchronizers 470
8.6.l Interface Protocol Asynchronous Cell 472
8.7 Mixed Operating Mode Asynchronous Circuits 474
Summary 477
References 478
Glossary 479
Questions and Problems 480
CHAPTER 9 Programmable Logic and Memory
Introduction 485
9.1 Memory 486
9.1.1 ROM, PROM, and EPROM 486,
9.2 Using an EPROM to Realize a Sequential Circuit 49l
9.3 Programmable Logic Devices 495
9.3.l Programmable Logic Array (PLA) 496
9.3.2 Programmable Array Logic 498
9.3.3 Designing an Up-Down Decade Counter Using a PAL 502
9.3.4 Generic Array Logic 507
9.3.5 Designing a Synchronous Sequential Circuit Using a GAL 509
9.4 Erasable Programmable Logic Devices 5l4
9.4.l Altera EP600 EPLD 5l7
9.4.2 Sequential Circuit Realization Using an EP600 5l9
9.5 PLD Computer-Aided Design 523
9.5.l PLD Realization of Combinational Logic 525
9:5.2 Realizing Truth Tables Using a PLD Language 529
9.5.3 Realizing Flip-Flops Using a PLD Language 530
9.5.4 Realizing State Machines Using a PLD Language 530
9.6 Field Programmable Gate Arrays 534
9.6.l Xilinx FPGA 535
9.6.2 System Development Tools for the Xilinx FPGA 542
9.6.3 Xilinx Macro Library 543
9.6.4 Actel FPGA 543
Summary 549
References 550
Glossary 55l
Questions and Problems 552
CHAPTER l0 Digital Integrated Circuits
Introduction 556
l0.1 Diodes as Switches 556
l0.l.l Diode Gates 558
l0.2 Bipolar Transistor Switch 56l
l0.3 Diode Transistor Logic 562
l0.4 Evolution from DTL to TTL 563
10.5 Transistor--Transistor Logic 565
l0.5.l TTL Circuit Operation 567
l0.5.2 TTL Specifications 569
l0.5.3 TTL Subfamilies 573
l0.5.4 Schottky Junctions 578
l0.5.5 Comparison of TTL Subfamily Specifications 579
l0.5.6 Open Collector TTL Circuits 580
l0.5.7 Tristate TTL Devices 584
l0.5.8 Mixed TTL Subfamily Fan-Out 585
l0.5.9 Other TTL Circuits 587
l0.6 Emitter-Coupled Logic 590
l0.6.1 Emitter-Coupled Logic Circuit 590
l0.6.2 ECL Specifications 594
l0.6.3 ECL to TTL and TTL to ECL Interfacing 595
l0.7 Complementary Metal Oxide Semiconductor 597
l0.7.l Field Effect Transistors 597
l0.7.2 MOSFETs 603
l0.7.3 MOSFET Logic Gates 606
l0.7.4 CMOS Logic Gates 609
l0.7.5 Power Dissipation for High-Speed CMOS 6l2
l0.7.6 Propagation Delay for High-Speed CMOS 6l3
l0.7.7 CMOS Noise Margins 613
l0.7.8 CMOS Subfamilies 613
Summary 6l5
References 615
Glossary 616
Questions and Problems 617
Appendix l TTL Analysis Spice Exercise
Appendix 2 Answers to Odd-Numbered Questions and Problems
Index
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